linux-kernel - Re: [PATCH v2 05/10] dt-bindings: riscv: Add andestech,cpu-intc to interrupt-controller

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Message-ID: <20231020-droop-decimeter-eb22d50d785c@spud>
Date:   Fri, 20 Oct 2023 10:54:16 +0100
From:   Conor Dooley <conor@...nel.org>
To:     Yu Chien Peter Lin <peterlin@...estech.com>
Cc:     robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
        paul.walmsley@...ive.com, palmer@...belt.com,
        aou@...s.berkeley.edu, linux-riscv@...ts.infradead.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        prabhakar.mahadev-lad.rj@...renesas.com, tim609@...estech.com,
        dylan@...estech.com, locus84@...estech.com, dminus@...estech.com
Subject: Re: [PATCH v2 05/10] dt-bindings: riscv: Add andestech,cpu-intc to
 interrupt-controller

Yo,

On Thu, Oct 19, 2023 at 09:59:05PM +0800, Yu Chien Peter Lin wrote:
> Add "andestech,cpu-intc" compatible string for Andes INTC which
> provides Andes-specific IRQ chip functions.

You need to provide some information as to what differentiates your intc
from the regular one, not mention linux driver specifics.

> 
> Signed-off-by: Yu Chien Peter Lin <peterlin@...estech.com>
> ---
> Changes v1 -> v2:
>   - New patch
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 97e8441eda1c..5b216e11c69f 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -99,7 +99,9 @@ properties:
>          const: 1
>  
>        compatible:
> -        const: riscv,cpu-intc
> +        enum:
> +          - riscv,cpu-intc
> +          - andestech,cpu-intc

Should the andestech intc not fall back to the generic intc compatible?
The generic one appears to implement a compatible subset of the features
that yours does.

Cheers,
Conor.

>  
>        interrupt-controller: true
>  
> -- 
> 2.34.1
> 
> 

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