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Message-ID: <20231020-barley-rosy-92c3688cd515@spud>
Date: Fri, 20 Oct 2023 15:21:15 +0100
From: Conor Dooley <conor@...nel.org>
To: William Qiu <william.qiu@...rfivetech.com>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, linux-pwm@...r.kernel.org,
Emil Renner Berthing <kernel@...il.dk>,
Rob Herring <robh+dt@...nel.org>,
Thierry Reding <thierry.reding@...il.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>,
Hal Feng <hal.feng@...rfivetech.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>
Subject: Re: [PATCH v6 1/4] dt-bindings: pwm: Add OpenCores PWM module
Krzysztof, William,
On Fri, Oct 20, 2023 at 06:37:38PM +0800, William Qiu wrote:
> Add documentation to describe OpenCores Pulse Width Modulation
> controller driver.
>
> Signed-off-by: William Qiu <william.qiu@...rfivetech.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Reviewed-by: Hal Feng <hal.feng@...rfivetech.com>
> ---
> .../bindings/pwm/opencores,pwm-ocores.yaml | 53 +++++++++++++++++++
> 1 file changed, 53 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml
>
> diff --git a/Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml b/Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml
> new file mode 100644
> index 000000000000..0f6a3434f155
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml
> @@ -0,0 +1,53 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pwm/opencores,pwm-ocores.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: OpenCores PWM controller
> +
> +maintainers:
> + - William Qiu <william.qiu@...rfivetech.com>
> +
> +description:
> + OpenCores PTC ip core contains a PWM controller. When operating in PWM mode, the PTC core
> + generates binary signal with user-programmable low and high periods. All PTC counters and
> + registers are 32-bit.
> +
> +allOf:
> + - $ref: pwm.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - opencores,pwm-ocores
What does the extra "ocores" suffix add, when it just repeats the vendor
prefix?
> + - starfive,jh71x0-pwm
Krzysztof, did you approve this generic compatible?
And the whole thing looks like it should really be something like
items:
- enum:
- starfive,jh7100-pwm
- starfive,jh7110-pwm
- const: opencores,pwm
Cheers,
Conor.
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + "#pwm-cells":
> + const: 3
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + pwm@...90000 {
> + compatible = "opencores,pwm-ocores";
> + reg = <0x12490000 0x10000>;
> + clocks = <&clkgen 181>;
> + resets = <&rstgen 109>;
> + #pwm-cells = <3>;
> + };
> --
> 2.34.1
>
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