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Message-ID: <20231021094718.fgy32sevjjdx2d3c@basti-XPS-13-9310>
Date: Sat, 21 Oct 2023 11:47:18 +0200
From: Sebastian Fricke <sebastian.fricke@...labora.com>
To: Yunfei Dong <yunfei.dong@...iatek.com>
Cc: NĂcolas F . R . A . Prado
<nfraprado@...labora.com>,
Nicolas Dufresne <nicolas.dufresne@...labora.com>,
Hans Verkuil <hverkuil-cisco@...all.nl>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
Benjamin Gaignard <benjamin.gaignard@...labora.com>,
Nathan Hebert <nhebert@...omium.org>,
Chen-Yu Tsai <wenst@...omium.org>,
Hsin-Yi Wang <hsinyi@...omium.org>,
Fritz Koenig <frkoenig@...omium.org>,
Daniel Vetter <daniel@...ll.ch>,
Steve Cho <stevecho@...omium.org>, linux-media@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [PATCH 3/7] media: mediatek: vcodec: Setting the supported h265
level for each platform
Hey Yunfei,
please replace Setting with Set in the title.
On 21.10.2023 11:25, Sebastian Fricke wrote:
>Hey Yunfei,
>
>On 16.10.2023 14:43, Yunfei Dong wrote:
>>The supported resolution and fps of different platforms are not the
>>same. Need to set the supported level according to the chip name.
>
>I would suggest the following rewording:
>
>Set the maximum H265 codec level for each platform.
>The various mediatek platforms support different levels for decoding,
>the level of the codec limits among others the maximum resolution, bit
>rate and frame rate for the decoder.
>
>With that you can add:
>Reviewed-by: Sebastian Fricke <sebastian.fricke@...labora.com>
>
>Regards,
>Sebastian
>
>>Signed-off-by: Yunfei Dong <yunfei.dong@...iatek.com>
>>---
>>.../vcodec/decoder/mtk_vcodec_dec_stateless.c | 28 +++++++++++++++++++
>>1 file changed, 28 insertions(+)
>>
>>diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c
>>index f4af81bddc58..1fdb21dbacb8 100644
>>--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c
>>+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c
>>@@ -147,6 +147,16 @@ static const struct mtk_stateless_control mtk_stateless_controls[] = {
>> },
>> .codec_type = V4L2_PIX_FMT_HEVC_SLICE,
>> },
>>+ {
>>+ .cfg = {
>>+ .id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
>>+ .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
>>+ .def = V4L2_MPEG_VIDEO_HEVC_LEVEL_4,
>>+ .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1,
>>+ },
>>+ .codec_type = V4L2_PIX_FMT_HEVC_SLICE,
>>+ },
>>+
>> {
>> .cfg = {
>> .id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
>>@@ -549,6 +559,20 @@ static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg,
>> };
>>}
>>
>>+static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg,
>>+ struct mtk_vcodec_dec_ctx *ctx)
>>+{
>>+ switch (ctx->dev->chip_name) {
>>+ case MTK_VDEC_MT8188:
>>+ case MTK_VDEC_MT8195:
>>+ cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1;
>>+ break;
>>+ default:
>>+ cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4;
>>+ break;
>>+ };
>>+}
>>+
>>static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg,
>> struct mtk_vcodec_dec_ctx *ctx)
>>{
>>@@ -557,6 +581,10 @@ static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg,
>> mtk_vcodec_dec_fill_h264_level(cfg, ctx);
>> mtk_v4l2_vdec_dbg(3, ctx, "h264 supported level: %lld %lld", cfg->max, cfg->def);
>> break;
>>+ case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL:
>>+ mtk_vcodec_dec_fill_h265_level(cfg, ctx);
>>+ mtk_v4l2_vdec_dbg(3, ctx, "h265 supported level: %lld %lld", cfg->max, cfg->def);
>>+ break;
>> default:
>> break;
>> };
>>--
>>2.18.0
>>
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