[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20231022151858.2479969-3-peterlin@andestech.com>
Date: Sun, 22 Oct 2023 23:18:47 +0800
From: Yu Chien Peter Lin <peterlin@...estech.com>
To: <acme@...nel.org>, <adrian.hunter@...el.com>,
<ajones@...tanamicro.com>, <alexander.shishkin@...ux.intel.com>,
<andre.przywara@....com>, <anup@...infault.org>,
<aou@...s.berkeley.edu>, <atishp@...shpatra.org>,
<conor+dt@...nel.org>, <conor.dooley@...rochip.com>,
<conor@...nel.org>, <devicetree@...r.kernel.org>,
<dminus@...estech.com>, <evan@...osinc.com>,
<geert+renesas@...der.be>, <guoren@...nel.org>, <heiko@...ech.de>,
<irogers@...gle.com>, <jernej.skrabec@...il.com>,
<jolsa@...nel.org>, <jszhang@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <linux-perf-users@...r.kernel.org>,
<linux-renesas-soc@...r.kernel.org>,
<linux-riscv@...ts.infradead.org>, <linux-sunxi@...ts.linux.dev>,
<locus84@...estech.com>, <magnus.damm@...il.com>,
<mark.rutland@....com>, <mingo@...hat.com>, <n.shubin@...ro.com>,
<namhyung@...nel.org>, <palmer@...belt.com>,
<paul.walmsley@...ive.com>, <peterlin@...estech.com>,
<peterz@...radead.org>, <prabhakar.mahadev-lad.rj@...renesas.com>,
<rdunlap@...radead.org>, <robh+dt@...nel.org>,
<samuel@...lland.org>, <sunilvl@...tanamicro.com>,
<tglx@...utronix.de>, <tim609@...estech.com>, <uwu@...nowy.me>,
<wens@...e.org>, <will@...nel.org>, <ycliang@...estech.com>
Subject: [RFC PATCH v3 02/13] irqchip/riscv-intc: Allow large non-standard hwirq number
Currently, the implementation of the RISC-V INTC driver uses the
interrupt cause as hwirq and has a limitation of supporting a
maximum of 64 hwirqs. However, according to the privileged spec,
interrupt causes >= 16 are defined for platform use.
This limitation prevents us from fully utilizing the available
local interrupt sources. Additionally, the hwirqs used on RISC-V
are sparse, with only interrupt numbers 1, 5 and 9 (plus Sscofpmf
or T-Head's PMU irq) being currently used for supervisor mode.
The patch switches to using irq_domain_create_tree() which
creates the radix tree map, allowing us to handle a larger
number of hwirqs.
Signed-off-by: Yu Chien Peter Lin <peterlin@...estech.com>
Reviewed-by: Charles Ci-Jyun Wu <dminus@...estech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@...estech.com>
---
Changes v1 -> v2:
- Fixed irq mapping failure checking (suggested by Clément and Anup)
Changes v2 -> v3:
- No change
---
drivers/irqchip/irq-riscv-intc.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index e8d01b14ccdd..79d049105384 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -24,10 +24,8 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
{
unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
- if (unlikely(cause >= BITS_PER_LONG))
- panic("unexpected interrupt cause");
-
- generic_handle_domain_irq(intc_domain, cause);
+ if (generic_handle_domain_irq(intc_domain, cause))
+ pr_warn("Failed to handle interrupt (cause: %ld)\n", cause);
}
/*
@@ -117,8 +115,8 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
{
int rc;
- intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG,
- &riscv_intc_domain_ops, NULL);
+ intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops,
+ NULL);
if (!intc_domain) {
pr_err("unable to add IRQ domain\n");
return -ENXIO;
@@ -132,8 +130,6 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
- pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
-
return 0;
}
--
2.34.1
Powered by blists - more mailing lists