lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <7d40c242-7779-45de-83c5-06db9983dae1@linaro.org>
Date:   Sun, 22 Oct 2023 18:12:15 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Devarsh Thakkar <devarsht@...com>,
        Sebastian Fricke <sebastian.fricke@...labora.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        NXP Linux Team <linux-imx@....com>,
        Conor Dooley <conor+dt@...nel.org>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        Jackson Lee <jackson.lee@...psnmedia.com>,
        Hans Verkuil <hverkuil@...all.nl>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Rob Herring <robh+dt@...nel.org>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        Shawn Guo <shawnguo@...nel.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Nas Chung <nas.chung@...psnmedia.com>,
        Fabio Estevam <festevam@...il.com>
Cc:     linux-media@...r.kernel.org, Tomasz Figa <tfiga@...omium.org>,
        linux-kernel@...r.kernel.org,
        Nicolas Dufresne <nicolas.dufresne@...labora.com>,
        kernel@...labora.com, Robert Beckett <bob.beckett@...labora.com>,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        Darren Etheridge <detheridge@...com>,
        "Bajjuri, Praneeth" <praneeth@...com>,
        "Raghavendra, Vignesh" <vigneshr@...com>,
        "Bhatia, Aradhya" <a-bhatia1@...com>,
        "Luthra, Jai" <j-luthra@...com>,
        "Brnich, Brandon" <b-brnich@...com>,
        "Pothukuchi, Vijay" <vijayp@...com>
Subject: Re: [PATCH v13 6/8] media: dt-bindings: wave5: add Chips&Media 521c
 codec IP support

On 17/10/2023 15:39, Devarsh Thakkar wrote:
>> +required:
>> +  - compatible
>> +  - reg
>> +  - clocks
>> +  - interrupts
>> +
> 
> Is it possible to keep interrupts property as optional given HW can still work
> without it if SW does polling of ISR using registers?
> 
> The reason to ask is in TI AM62A SoC (which also uses this codec) there is an
> SoC errata of missing interrupt line to A53 and we are using SW based polling
> locally to run the driver.
> 
> We were planning to upstream that SW based polling support patch in CnM driver
> once this base initial driver patch series gets merged, but just wanted to
> check if upfront it is possible to have interrupts property as optional so
> that we don't have to change the binding doc again to make it optional later on.
> 
> Also note that the polling patch won't be specific to AM62A, other SoC's too
> which use this wave5 hardware if they want can enable polling by choice (by
> removing interrupt property)
> 
> Could you please share your opinion on this ?

You know, if you do not have interrupt line connected, how could it be
required, right? If the hardware does not require interrupt to be
connected then bindings should not require it.

Best regards,
Krzysztof

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ