linux-kernel - Re: [PATCH v3 00/13] Support Andes PMU extension

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20231022-cabana-crate-503b6e8d0481@spud>
Date:   Sun, 22 Oct 2023 19:00:28 +0100
From:   Conor Dooley <conor@...nel.org>
To:     Yu Chien Peter Lin <peterlin@...estech.com>
Cc:     acme@...nel.org, adrian.hunter@...el.com, ajones@...tanamicro.com,
        alexander.shishkin@...ux.intel.com, andre.przywara@....com,
        anup@...infault.org, aou@...s.berkeley.edu, atishp@...shpatra.org,
        conor+dt@...nel.org, conor.dooley@...rochip.com,
        devicetree@...r.kernel.org, dminus@...estech.com,
        evan@...osinc.com, geert+renesas@...der.be, guoren@...nel.org,
        heiko@...ech.de, irogers@...gle.com, jernej.skrabec@...il.com,
        jolsa@...nel.org, jszhang@...nel.org,
        krzysztof.kozlowski+dt@...aro.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-perf-users@...r.kernel.org,
        linux-renesas-soc@...r.kernel.org, linux-riscv@...ts.infradead.org,
        linux-sunxi@...ts.linux.dev, locus84@...estech.com,
        magnus.damm@...il.com, mark.rutland@....com, mingo@...hat.com,
        n.shubin@...ro.com, namhyung@...nel.org, palmer@...belt.com,
        paul.walmsley@...ive.com, peterz@...radead.org,
        prabhakar.mahadev-lad.rj@...renesas.com, rdunlap@...radead.org,
        robh+dt@...nel.org, samuel@...lland.org, sunilvl@...tanamicro.com,
        tglx@...utronix.de, tim609@...estech.com, uwu@...nowy.me,
        wens@...e.org, will@...nel.org, ycliang@...estech.com
Subject: Re: [PATCH v3 00/13] Support Andes PMU extension

Hey,

On Sun, Oct 22, 2023 at 11:18:45PM +0800, Yu Chien Peter Lin wrote:
> Hi All,
> 
> This patch series introduces the Andes PMU extension, which serves
> the same purpose as Sscofpmf. In this version we use FDT-based
> probing and the CONFIG_ANDES_CUSTOM_PMU to enable perf sampling
> and filtering support.
> 
> Its non-standard local interrupt is assigned to bit 18 in the
> custom S-mode local interrupt enable/pending registers (slie/slip),
> while the interrupt cause is (256 + 18).
> 
> The feature needs the PMU device registered in OpenSBI.
> The OpenSBI and Linux patches can be found on Andes Technology GitHub
> - https://github.com/andestech/opensbi/commits/andes-pmu-support-v2
> - https://github.com/andestech/linux/commits/andes-pmu-support-v3
> 
> The PMU device tree node used on AX45MP:
> - https://github.com/andestech/opensbi/blob/andes-pmu-support-v2/docs/pmu_support.md#example-3
> 
> Tested hardware:
> - ASUS  Tinker-V (RZ/Five, AX45MP single core)
> - Andes AE350    (AX45MP quad core)
> 
> Locus Wei-Han Chen (1):
>   riscv: andes: Support symbolic FW and HW raw events
> 
> Yu Chien Peter Lin (12):
>   riscv: errata: Rename defines for Andes
>   irqchip/riscv-intc: Allow large non-standard hwirq number
>   irqchip/riscv-intc: Introduce Andes IRQ chip
>   dt-bindings: riscv: Add Andes interrupt controller compatible string
>   riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes
>     INTC
>   perf: RISC-V: Eliminate redundant IRQ enable/disable operations
>   RISC-V: Move T-Head PMU to CPU feature alternative framework
>   perf: RISC-V: Introduce Andes PMU for perf event sampling
>   dt-bindings: riscv: Add T-Head PMU extension description
>   dt-bindings: riscv: Add Andes PMU extension description
>   riscv: dts: allwinner: Add T-Head PMU extension
>   riscv: dts: renesas: Add Andes PMU extension

You only sent 5 of these patches FYI.

Download attachment "signature.asc" of type "application/pgp-signature" (229 bytes)