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Message-ID: <219ae3d7-0c75-49c0-b791-5623894ba318@lunn.ch>
Date: Tue, 24 Oct 2023 00:43:05 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Parthiban Veerasooran <Parthiban.Veerasooran@...rochip.com>
Cc: davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
pabeni@...hat.com, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
corbet@....net, steen.hegelund@...rochip.com,
rdunlap@...radead.org, horms@...nel.org, casper.casan@...il.com,
netdev@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org,
horatiu.vultur@...rochip.com, Woojung.Huh@...rochip.com,
Nicolas.Ferre@...rochip.com, UNGLinuxDriver@...rochip.com,
Thorsten.Kummermehr@...rochip.com
Subject: Re: [PATCH net-next v2 2/9] net: ethernet: oa_tc6: implement mac-phy
software reset
> + ret = oa_tc6_perform_ctrl(tc6, RESET, ®val, 1, true, true);
> + ret = oa_tc6_perform_ctrl(tc6, RESET, ®val, 1, true, false);
Just looking at this, it is not clear what these true/false mean. Maybe add some #defines
#define TC6_READ true
#define TC6_WRITE false
#define TC6_PROTECTED true
#define TC6_UNPROTECTED false
> + if (ret)
> + return ret;
> +
> + /* The chip completes a reset in 3us, we might get here earlier than
> + * that, as an added margin we'll conditionally sleep 5us.
> + */
> + udelay(5);
> +
> + ret = oa_tc6_perform_ctrl(tc6, STATUS0, ®val, 1, false, false);
> + if (ret)
> + return ret;
> +
> + /* Check for reset complete interrupt status */
> + if (regval & RESETC) {
> + regval = RESETC;
People don't always agree, but i found STATUS0_RESETC easier to see
you have the correct bit for the register you just read.
Andrew
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