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Message-Id: <20231023082911.23242-13-luxu.kernel@bytedance.com>
Date:   Mon, 23 Oct 2023 16:29:11 +0800
From:   Xu Lu <luxu.kernel@...edance.com>
To:     paul.walmsley@...ive.com, palmer@...belt.com,
        aou@...s.berkeley.edu, tglx@...utronix.de, maz@...nel.org,
        anup@...infault.org, atishp@...shpatra.org
Cc:     dengliang.1214@...edance.com, liyu.yukiteru@...edance.com,
        sunjiadong.lff@...edance.com, xieyongji@...edance.com,
        lihangjing@...edance.com, chaiwen.cc@...edance.com,
        linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
        Xu Lu <luxu.kernel@...edance.com>
Subject: [RFC 12/12] riscv: Enable CONFIG_RISCV_PSEUDO_NMI in default

This commit enables CONFIG_RISCV_PSEUDO_NMI in default. Now pseudo NMI
feature is defaultly enabled on RISC-V.

Signed-off-by: Xu Lu <luxu.kernel@...edance.com>
---
 arch/riscv/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 487e4293f31e..ecccdc91563f 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -672,7 +672,7 @@ config RISCV_BOOT_SPINWAIT
 config RISCV_PSEUDO_NMI
 	bool "Support for NMI-like interrupts"
 	depends on !RISCV_M_MODE
-	default n
+	default y
 	help
 	  Adds support for mimicking Non-Maskable Interrupts through the use of
 	  CSR_IE register.
-- 
2.20.1

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