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Message-ID: <a55df8fa-122f-4721-94ac-5a2ca4cc7e26@gmail.com>
Date: Mon, 23 Oct 2023 18:49:40 -0700
From: Florian Fainelli <f.fainelli@...il.com>
To: Gregory CLEMENT <gregory.clement@...tlin.com>,
Paul Burton <paulburton@...nel.org>,
Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
linux-mips@...r.kernel.org, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Cc: Vladimir Kondratiev <vladimir.kondratiev@...el.com>,
Tawfik Bayouk <tawfik.bayouk@...ileye.com>,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
Théo Lebrun <theo.lebrun@...tlin.com>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH 01/11] MIPS: compressed: Use correct instruction for 64
bit code
On 10/4/2023 9:10 AM, Gregory CLEMENT wrote:
> The code clearing BSS already use macro or use correct instruction
> depending id the CPU is 32 bits or 64 bits.
s/id/if/
> However, a few
> instructions remained 32 bits only.
>
> By using the accurate MACRO, it is now possible to deal with memory
> address beyond 32 bits. As a side effect, when using 64bits processor,
> it also divides the loop number needed to clear the BSS by 2.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@...tlin.com>
Reviewed-by: Florian Fainelli <florian.fainelli@...adcom.com>
> ---
> arch/mips/boot/compressed/head.S | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
> index 5795d0af1e1b..d237a834b85e 100644
> --- a/arch/mips/boot/compressed/head.S
> +++ b/arch/mips/boot/compressed/head.S
> @@ -25,8 +25,8 @@
> /* Clear BSS */
> PTR_LA a0, _edata
> PTR_LA a2, _end
> -1: sw zero, 0(a0)
> - addiu a0, a0, 4
> +1: PTR_S zero, 0(a0)
> + PTR_ADDIU a0, a0, PTRSIZE
> bne a2, a0, 1b
>
> PTR_LA a0, (.heap) /* heap address */
--
Florian
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