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Message-ID: <169817619092.434632.12338153362080945824.robh@kernel.org>
Date:   Tue, 24 Oct 2023 14:36:31 -0500
From:   Rob Herring <robh@...nel.org>
To:     Alvin Šipraga <alvin@...s.dk>
Cc:     linux-clk@...r.kernel.org, Conor Dooley <conor+dt@...nel.org>,
        Jacob Siverskog <jacob@...nage.engineering>,
        Stephen Boyd <sboyd@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Michael Turquette <mturquette@...libre.com>,
        Rabeeh Khoury <rabeeh@...id-run.com>,
        devicetree@...r.kernel.org, Rob Herring <robh+dt@...nel.org>,
        Sergej Sawazki <sergej@...dac.com>,
        Alvin Šipraga <alsi@...g-olufsen.dk>,
        linux-kernel@...r.kernel.org,
        Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>
Subject: Re: [PATCH v5 2/3] dt-bindings: clock: si5351: add PLL reset mode
 property


On Fri, 20 Oct 2023 13:34:15 +0200, Alvin Šipraga wrote:
> From: Alvin Šipraga <alsi@...g-olufsen.dk>
> 
> For applications where the PLL must be adjusted without glitches in the
> clock output(s), a new silabs,pll-reset-mode property is added. It
> can be used to specify whether or not the PLL should be reset after
> adjustment. Resetting is known to cause glitches.
> 
> For compatibility with older device trees, it must be assumed that the
> default PLL reset mode is to unconditionally reset after adjustment.
> 
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>
> Cc: Rabeeh Khoury <rabeeh@...id-run.com>
> Cc: Jacob Siverskog <jacob@...nage.engineering>
> Cc: Sergej Sawazki <sergej@...dac.com>
> Signed-off-by: Alvin Šipraga <alsi@...g-olufsen.dk>
> ---
>  .../devicetree/bindings/clock/silabs,si5351.yaml   | 24 ++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 

Reviewed-by: Rob Herring <robh@...nel.org>

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