linux-kernel - Re: [PATCH 2/2] perf/x86/amd: Don't allow pre-emption in amd_pmu_lbr

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Message-ID: <ZTd6BYr17ycdHR2a@gmail.com>
Date:   Tue, 24 Oct 2023 10:02:13 +0200
From:   Ingo Molnar <mingo@...nel.org>
To:     Mario Limonciello <mario.limonciello@....com>
Cc:     Peter Zijlstra <peterz@...radead.org>,
        Borislav Petkov <bp@...en8.de>,
        Thomas Gleixner <tglx@...utronix.de>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        Sandipan Das <sandipan.das@....com>,
        "H . Peter Anvin" <hpa@...or.com>, linux-kernel@...r.kernel.org,
        x86@...nel.org, linux-pm@...r.kernel.org, rafael@...nel.org,
        pavel@....cz, linux-perf-users@...r.kernel.org,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...nel.org>,
        Namhyung Kim <namhyung@...nel.org>,
        Ian Rogers <irogers@...gle.com>,
        Adrian Hunter <adrian.hunter@...el.com>
Subject: Re: [PATCH 2/2] perf/x86/amd: Don't allow pre-emption in
 amd_pmu_lbr_reset()


* Mario Limonciello <mario.limonciello@....com> wrote:

> Fixes a BUG reported during suspend to ram testing.
> 
> ```
> [  478.274752] BUG: using smp_processor_id() in preemptible [00000000] code: rtcwake/2948
> [  478.274754] caller is amd_pmu_lbr_reset+0x19/0xc0
> ```
> 
> Cc: stable@...r.kernel.org # 6.1+
> Fixes: ca5b7c0d9621 ("perf/x86/amd/lbr: Add LbrExtV2 branch record support")
> Signed-off-by: Mario Limonciello <mario.limonciello@....com>
> ---
>  arch/x86/events/amd/lbr.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/events/amd/lbr.c b/arch/x86/events/amd/lbr.c
> index eb31f850841a..5b98e8c7d8b7 100644
> --- a/arch/x86/events/amd/lbr.c
> +++ b/arch/x86/events/amd/lbr.c
> @@ -321,7 +321,7 @@ int amd_pmu_lbr_hw_config(struct perf_event *event)
>  
>  void amd_pmu_lbr_reset(void)
>  {
> -	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
> +	struct cpu_hw_events *cpuc = get_cpu_ptr(&cpu_hw_events);
>  	int i;
>  
>  	if (!x86_pmu.lbr_nr)
> @@ -335,6 +335,7 @@ void amd_pmu_lbr_reset(void)
>  
>  	cpuc->last_task_ctx = NULL;
>  	cpuc->last_log_id = 0;
> +	put_cpu_ptr(&cpu_hw_events);
>  	wrmsrl(MSR_AMD64_LBR_SELECT, 0);
>  }

Weird, amd_pmu_lbr_reset() is called from these places:

  - amd_pmu_lbr_sched_task(): during task sched-in during 
    context-switching, this should already have preemption disabled.

  - amd_pmu_lbr_add(): this gets indirectly called by amd_pmu::add 
    (amd_pmu_add_event()), called by event_sched_in(), which too should have 
    preemption disabled.

I clearly must have missed some additional place it gets called in.

Could you please cite the full log of the amd_pmu_lbr_reset() call that 
caused the critical section warning?

Thanks,

	Ingo