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Message-ID: <CAA8EJpoeV9bqX=mZZ3RMrzqGQ+Hq1Nc_pr=vBjJbarNC4J+FRQ@mail.gmail.com>
Date: Wed, 25 Oct 2023 20:59:13 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Mukesh Ojha <quic_mojha@...cinc.com>
Cc: agross@...nel.org, andersson@...nel.org, konrad.dybcio@...aro.org,
lee@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 2/4] arm64: dts: qcom: sm8250: Add TCSR halt register space
On Wed, 25 Oct 2023 at 20:07, Mukesh Ojha <quic_mojha@...cinc.com> wrote:
>
> Enable download mode for sm8250 which can help collect
> ramdump for this SoC.
>
> Signed-off-by: Mukesh Ojha <quic_mojha@...cinc.com>
> ---
> Changes in v2:
> - Improved commit text.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
>
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index be970472f6c4..76f470a78608 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -671,6 +671,7 @@
> firmware {
> scm: scm {
> compatible = "qcom,scm-sm8250", "qcom,scm";
> + qcom,dload-mode = <&tcsr 0x13000>;
> #reset-cells = <1>;
> };
> };
> @@ -2543,6 +2544,11 @@
> #hwlock-cells = <1>;
> };
>
> + tcsr: syscon@...0000 {
> + compatible = "qcom,sm8250-tcsr", "syscon";
> + reg = <0x0 0x1fc0000 0x0 0x30000>;
> + };
> +
> wsamacro: codec@...0000 {
> compatible = "qcom,sm8250-lpass-wsa-macro";
> reg = <0 0x03240000 0 0x1000>;
> --
> 2.7.4
>
--
With best wishes
Dmitry
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