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Message-Id: <20231025183644.8735-2-jerry.shih@sifive.com> Date: Thu, 26 Oct 2023 02:36:33 +0800 From: Jerry Shih <jerry.shih@...ive.com> To: paul.walmsley@...ive.com, palmer@...belt.com, aou@...s.berkeley.edu, herbert@...dor.apana.org.au, davem@...emloft.net Cc: andy.chiu@...ive.com, greentime.hu@...ive.com, conor.dooley@...rochip.com, guoren@...nel.org, bjorn@...osinc.com, heiko@...ech.de, ebiggers@...nel.org, ardb@...nel.org, phoebe.chen@...ive.com, hongrong.hsu@...ive.com, linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, linux-crypto@...r.kernel.org Subject: [PATCH 01/12] RISC-V: add helper function to read the vector VLEN From: Heiko Stuebner <heiko.stuebner@...ll.eu> VLEN describes the length of each vector register and some instructions need specific minimal VLENs to work correctly. The vector code already includes a variable riscv_v_vsize that contains the value of "32 vector registers with vlenb length" that gets filled during boot. vlenb is the value contained in the CSR_VLENB register and the value represents "VLEN / 8". So add riscv_vector_vlen() to return the actual VLEN value for in-kernel users when they need to check the available VLEN. Signed-off-by: Heiko Stuebner <heiko.stuebner@...ll.eu> Signed-off-by: Jerry Shih <jerry.shih@...ive.com> --- arch/riscv/include/asm/vector.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 9fb2dea66abd..1fd3e5510b64 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -244,4 +244,15 @@ void kernel_vector_allow_preemption(void); #define kernel_vector_allow_preemption() do {} while (0) #endif +/* + * Return the implementation's vlen value. + * + * riscv_v_vsize contains the value of "32 vector registers with vlenb length" + * so rebuild the vlen value in bits from it. + */ +static inline int riscv_vector_vlen(void) +{ + return riscv_v_vsize / 32 * 8; +} + #endif /* ! __ASM_RISCV_VECTOR_H */ -- 2.28.0
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