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Date:   Wed, 25 Oct 2023 11:56:41 -0700
From:   Emil Renner Berthing <>
Cc:     Conor Dooley <>, Rob Herring <>,
        Krzysztof Kozlowski <>,
        Palmer Dabbelt <>,
        Paul Walmsley <>,
        Emil Renner Berthing <>
Subject: [PATCH 3/4] dt-bindings: cache: sifive,ccache0: Add sifive,cache-ops property

This cache controller also supports flushing cache lines by writing
their address to a register. This can be used for cache management on
SoCs with non-coherent DMAs that predate the RISC-V Zicbom extension
such as the StarFive JH7100 SoC.

Signed-off-by: Emil Renner Berthing <>
 Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
index 7e8cebe21584..36ae6f48ce0b 100644
--- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
@@ -81,6 +81,11 @@ properties:
       The reference to the reserved-memory for the L2 Loosely
Integrated Memory region.
       The reserved memory node should be defined as per the bindings
in reserved-memory.txt.

+  sifive,cache-ops:
+    type: boolean
+    description: |
+      Use this cache controller for non-standard cache management operations.
   - $ref: /schemas/cache-controller.yaml#


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