linux-kernel - Re: [PATCH 0/4] soc: sifive: ccache: Add StarFive JH7100 support

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Date:   Wed, 25 Oct 2023 12:06:50 -0700
From:   Emil Renner Berthing <emil.renner.berthing@...onical.com>
To:     Emil Renner Berthing <emil.renner.berthing@...onical.com>,
        linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Cc:     Conor Dooley <conor@...nel.org>, Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>
Subject: Re: [PATCH 0/4] soc: sifive: ccache: Add StarFive JH7100 support

Emil Renner Berthing wrote:
> This series adds support for the StarFive JH7100 SoC to the SiFive cache
> controller driver. The JH7100 was a "development version" of the JH7110
> used on the BeagleV Starlight and VisionFive V1 boards.  It has
> non-coherent peripheral DMAs but was designed before the standard RISC-V
> Zicbom extension, so it neeeds support in this driver for non-standard
> cache management.

Ugh, sorry about the broken threading and From vs. Signed-off-by's.
Will fix in v2.

/Emil