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Date:   Wed, 25 Oct 2023 21:48:49 +0200
From:   Sebastian Reichel <sebastian.reichel@...labora.com>
To:     Stephen Boyd <sboyd@...nel.org>
Cc:     conor+dt@...nel.org, heiko@...ech.de, kever.yang@...k-chips.com,
        krzysztof.kozlowski+dt@...aro.org, mturquette@...libre.com,
        robh+dt@...nel.org, zhangqing@...k-chips.com,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-clk@...r.kernel.org, linux-rockchip@...ts.infradead.org,
        linux-kernel@...r.kernel.org, huangtao@...k-chips.com,
        andy.yan@...k-chips.com
Subject: Re: [PATCH v4 0/4] rockchip: add GATE_LINK

Hello Stephen,

On Mon, Oct 23, 2023 at 06:47:17PM -0700, Stephen Boyd wrote:
> Quoting Elaine Zhang (2023-10-18 00:01:40)
> > Recent Rockchip SoCs have a new hardware block called Native Interface
> > Unit (NIU), which gates clocks to devices behind them. These effectively
> > need two parent clocks.
> > Use GATE_LINK to handle this.
> 
> Why can't pm clks be used here? The qcom clk driver has been doing that
> for some time now. 
> 
>  $ git grep pm_clk_add -- drivers/clk/qcom/

Maybe I'm mistaken, but as far as I can tell this is adding the
dependency on controller level and only works because Qualcomm
has multiple separate clock controllers. In the Rockchip design
there is only one platform device.

Note, that the original downstream code from Rockchip actually used
pm_clk infrastructure by moving these clocks to separate platform
devices. I changed this when upstreaming the code, since that leaks
into DT and from DT point of view there should be only one clock
controller.

Greetings,

-- Sebastian

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