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Date:   Wed, 25 Oct 2023 11:03:54 +0300
From:   Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To:     Neil Armstrong <neil.armstrong@...aro.org>
Cc:     Rob Clark <robdclark@...il.com>,
        Abhinav Kumar <quic_abhinavk@...cinc.com>,
        Sean Paul <sean@...rly.run>,
        Marijn Suijten <marijn.suijten@...ainline.org>,
        David Airlie <airlied@...il.com>,
        Daniel Vetter <daniel@...ll.ch>,
        Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
        Maxime Ripard <mripard@...nel.org>,
        Thomas Zimmermann <tzimmermann@...e.de>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Jonathan Marek <jonathan@...ek.ca>,
        Krishna Manikandan <quic_mkrishn@...cinc.com>,
        linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
        freedreno@...ts.freedesktop.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 7/8] drm/msm: dsi: add support for DSI-PHY on SM8650

On Wed, 25 Oct 2023 at 10:35, Neil Armstrong <neil.armstrong@...aro.org> wrote:
>
> Add DSI PHY support for the SM8650 platform.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
> ---
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy.c     |  2 ++
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy.h     |  1 +
>  drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 27 +++++++++++++++++++++++++++
>  3 files changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index 05621e5e7d63..7612be6c3618 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -585,6 +585,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
>           .data = &dsi_phy_5nm_8450_cfgs },
>         { .compatible = "qcom,sm8550-dsi-phy-4nm",
>           .data = &dsi_phy_4nm_8550_cfgs },
> +       { .compatible = "qcom,sm8650-dsi-phy-4nm",
> +         .data = &dsi_phy_4nm_8650_cfgs },
>  #endif
>         {}
>  };
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index 8b640d174785..e4275d3ad581 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -62,6 +62,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
>  extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
>  extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
>  extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
> +extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs;
>
>  struct msm_dsi_dphy_timing {
>         u32 clk_zero;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index 3b1ed02f644d..c66193f2dc0d 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -1121,6 +1121,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = {
>         { .supply = "vdds", .init_load_uA = 37550 },
>  };
>
> +static const struct regulator_bulk_data dsi_phy_7nm_98000uA_regulators[] = {
> +       { .supply = "vdds", .init_load_uA = 98000 },
> +};
> +
>  static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = {
>         { .supply = "vdds", .init_load_uA = 97800 },
>  };
> @@ -1281,3 +1285,26 @@ const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = {
>         .num_dsi_phy = 2,
>         .quirks = DSI_PHY_7NM_QUIRK_V5_2,
>  };
> +
> +const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = {

So, this is the same as sm8550 config, just using 400 uA less? I
wonder if it makes sense to go for setting the regulator mode instead
of setting the load.

Nevertheless (unless you'd like to reuse sm8550 config entry):

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>

> +       .has_phy_lane = true,
> +       .regulator_data = dsi_phy_7nm_98000uA_regulators,
> +       .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators),
> +       .ops = {
> +               .enable = dsi_7nm_phy_enable,
> +               .disable = dsi_7nm_phy_disable,
> +               .pll_init = dsi_pll_7nm_init,
> +               .save_pll_state = dsi_7nm_pll_save_state,
> +               .restore_pll_state = dsi_7nm_pll_restore_state,
> +               .set_continuous_clock = dsi_7nm_set_continuous_clock,
> +       },
> +       .min_pll_rate = 600000000UL,
> +#ifdef CONFIG_64BIT
> +       .max_pll_rate = 5000000000UL,
> +#else
> +       .max_pll_rate = ULONG_MAX,
> +#endif
> +       .io_start = { 0xae95000, 0xae97000 },
> +       .num_dsi_phy = 2,
> +       .quirks = DSI_PHY_7NM_QUIRK_V5_2,
> +};
>
> --
> 2.34.1
>


-- 
With best wishes
Dmitry

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