lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 25 Oct 2023 11:39:50 +0000
From:   <Parthiban.Veerasooran@...rochip.com>
To:     <andrew@...n.ch>
CC:     <davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>,
        <pabeni@...hat.com>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
        <corbet@....net>, <Steen.Hegelund@...rochip.com>,
        <rdunlap@...radead.org>, <horms@...nel.org>,
        <casper.casan@...il.com>, <netdev@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-doc@...r.kernel.org>, <Horatiu.Vultur@...rochip.com>,
        <Woojung.Huh@...rochip.com>, <Nicolas.Ferre@...rochip.com>,
        <UNGLinuxDriver@...rochip.com>, <Thorsten.Kummermehr@...rochip.com>
Subject: Re: [PATCH net-next v2 2/9] net: ethernet: oa_tc6: implement mac-phy
 software reset

Hi Andrew,

On 24/10/23 4:13 am, Andrew Lunn wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
>> +     ret = oa_tc6_perform_ctrl(tc6, RESET, &regval, 1, true, true);
>> +     ret = oa_tc6_perform_ctrl(tc6, RESET, &regval, 1, true, false);
> 
> Just looking at this, it is not clear what these true/false mean. Maybe add some #defines
> 
> #define TC6_READ true
> #define TC6_WRITE false
> #define TC6_PROTECTED true
> #define TC6_UNPROTECTED false
Sure will do this.
> 
>> +     if (ret)
>> +             return ret;
>> +
>> +     /* The chip completes a reset in 3us, we might get here earlier than
>> +      * that, as an added margin we'll conditionally sleep 5us.
>> +      */
>> +     udelay(5);
>> +
>> +     ret = oa_tc6_perform_ctrl(tc6, STATUS0, &regval, 1, false, false);
>> +     if (ret)
>> +             return ret;
>> +
>> +     /* Check for reset complete interrupt status */
>> +     if (regval & RESETC) {
>> +             regval = RESETC;
> 
> People don't always agree, but i found STATUS0_RESETC easier to see
> you have the correct bit for the register you just read.
Do you want me to define STATUS0_RESETC instead of RESETC or is my 
understanding wrong?

Best Regards,
Parthiban V
> 
>          Andrew

Powered by blists - more mailing lists