linux-kernel - Re: [PATCH V2 5/6] pinctrl: sprd: Increase the range of register values

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Message-ID: <e8833e78-8678-e2fc-9de1-0b2531e179e1@linux.alibaba.com>
Date:   Thu, 26 Oct 2023 10:57:30 +0800
From:   Baolin Wang <baolin.wang@...ux.alibaba.com>
To:     xu lh <xulh0829@...il.com>
Cc:     Linhua Xu <Linhua.xu@...soc.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        Orson Zhai <orsonzhai@...il.com>,
        Chunyan Zhang <zhang.lyra@...il.com>,
        linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        Zhirong Qiu <zhirong.qiu@...soc.com>,
        Xiongpeng Wu <xiongpeng.wu@...soc.com>
Subject: Re: [PATCH V2 5/6] pinctrl: sprd: Increase the range of register
 values



On 10/25/2023 7:29 PM, xu lh wrote:
> On Tue, Sep 12, 2023 at 4:37 PM Baolin Wang <baolin.wang@...ux.alibaba.com>
> wrote:
> 
>>
>>
>> On 9/8/2023 1:51 PM, Linhua Xu wrote:
>>> From: Linhua Xu <Linhua.Xu@...soc.com>
>>>
>>> As the UNISOC pin controller version iterates, more registers are
>> required
>>> to meet new functional requirements. Thus modify them.
>>>
>>> Signed-off-by: Linhua Xu <Linhua.Xu@...soc.com>
>>> ---
>>>    drivers/pinctrl/sprd/pinctrl-sprd.h | 30 +++++++++++++++--------------
>>>    1 file changed, 16 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.h
>> b/drivers/pinctrl/sprd/pinctrl-sprd.h
>>> index a696f81ce663..5357874186fd 100644
>>> --- a/drivers/pinctrl/sprd/pinctrl-sprd.h
>>> +++ b/drivers/pinctrl/sprd/pinctrl-sprd.h
>>> @@ -7,30 +7,32 @@
>>>    #ifndef __PINCTRL_SPRD_H__
>>>    #define __PINCTRL_SPRD_H__
>>>
>>> +#include <linux/bits.h>
>>> +
>>>    struct platform_device;
>>>
>>> -#define NUM_OFFSET   (20)
>>> -#define TYPE_OFFSET  (16)
>>> -#define BIT_OFFSET   (8)
>>> -#define WIDTH_OFFSET (4)
>>> +#define NUM_OFFSET   22
>>> +#define TYPE_OFFSET  18
>>> +#define BIT_OFFSET   10
>>> +#define WIDTH_OFFSET 6
>>>
>>>    #define SPRD_PIN_INFO(num, type, offset, width, reg)        \
>>> -             (((num) & 0xFFF) << NUM_OFFSET |        \
>>> -              ((type) & 0xF) << TYPE_OFFSET |        \
>>> -              ((offset) & 0xFF) << BIT_OFFSET |      \
>>> -              ((width) & 0xF) << WIDTH_OFFSET |      \
>>> -              ((reg) & 0xF))
>>> +             (((num) & GENMASK(10, 0)) << NUM_OFFSET |       \
>>> +              ((type) & GENMASK(3, 0)) << TYPE_OFFSET |      \
>>> +              ((offset) & GENMASK(7, 0)) << BIT_OFFSET |     \
>>> +              ((width) & GENMASK(3, 0)) << WIDTH_OFFSET |    \
>>> +              ((reg) & GENMASK(5, 0)))
>>
>> Can you define some readable macro for the mask bits?
> 
> 
>>> okay. Do you think the following modification is okay?
> +#define PIN_ID         GENMASK(10, 0)
> +#define PIN_TYPE       GENMASK(3, 0)
> +#define FIELD_OFFSET   GENMASK(7, 0)
> +#define FIELD_WIDTH    GENMASK(3, 0)
> +#define PIN_REG                GENMASK(5, 0)

Looks better. To keep consistent, I perfer to something as below:
#define NUM_MASK xxx
#define TYPE_MASK xxx
#define BIT_MASK xxx
#define WIDTH_MASK xxx
#define REG_MASK xxx