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Message-ID: <20231026074148.7927-1-jay.buddhabhatti@amd.com>
Date: Thu, 26 Oct 2023 00:41:46 -0700
From: Jay Buddhabhatti <jay.buddhabhatti@....com>
To: <mturquette@...libre.com>, <sboyd@...nel.org>,
<michal.simek@....com>, <shubhrajyoti.datta@...inx.com>
CC: <linux-clk@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
Jay Buddhabhatti <jay.buddhabhatti@....com>
Subject: [PATCH v2 0/2] update for versal net platform
Update clock driver to support for Versal NET platforms.
Versal Net is a new AMD/Xilinx SoC.
V1 link: https://lore.kernel.org/lkml/20231016113002.15929-1-jay.buddhabhatti@amd.com/
V1->V2:
- Updated logic to use fls() to get max width of divider
- Added fixes tag in patch #1
Jay Buddhabhatti (2):
drivers: clk: zynqmp: calculate closest mux rate
drivers: clk: zynqmp: update divider round rate logic
drivers/clk/zynqmp/clk-mux-zynqmp.c | 2 +-
drivers/clk/zynqmp/divider.c | 66 +++--------------------------
2 files changed, 6 insertions(+), 62 deletions(-)
--
2.17.1
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