linux-kernel - Re: [RESEND PATCH v4 3/4] clk: qcom: camcc-sc8280xp: Add sc8280xp CAMCC

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Date:   Thu, 26 Oct 2023 13:21:23 +0200
From:   Konrad Dybcio <konrad.dybcio@...aro.org>
To:     Bryan O'Donoghue <bryan.odonoghue@...aro.org>,
        andersson@...nel.org, agross@...nel.org, mturquette@...libre.com,
        sboyd@...nel.org, dmitry.baryshkov@...aro.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
        jonathan@...ek.ca, quic_tdas@...cinc.com,
        vladimir.zapolskiy@...aro.org
Cc:     linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [RESEND PATCH v4 3/4] clk: qcom: camcc-sc8280xp: Add sc8280xp
 CAMCC



On 10/26/23 12:53, Bryan O'Donoghue wrote:
> Add the sc8280xp CAMCC driver which follows the sdm845 CAMCC lineage
> with additional CCI and IFE blocks and more granular clock parentage.
> 
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
> ---
[...]

> +static struct gdsc titan_top_gdsc;
> +
> +static struct gdsc bps_gdsc = {
> +	.gdscr = 0x7004,
> +	.pd = {
> +		.name = "bps_gdsc",
> +	},
> +	.flags = HW_CTRL | RETAIN_FF_ENABLE,
This should really be HW_CTRL_TRIGGER from [1]

and then downstream uses cam_bps_transfer_gdsc_control and
cam_bps_get_gdsc_control to control hw (fast) or sw (normal) mode

similarly in drivers/cam_icp/icp_hw/ipe_hw/ipe_soc.c for IPE

[...]

> +	/*
> +	 * Keep camcc_gdsc_clk always enabled:
> +	 */
> +	regmap_update_bits(regmap, 0xc1e4, BIT(0), 1);
/* Keep camcc_gdsc_clk always enabled */
regmap_update_bits(regmap, 0xc1e4, BIT(0), BIT(0));

[1] https://lore.kernel.org/linux-arm-msm/20230923115008.1698384-4-abel.vesa@linaro.org/

Konrad