linux-kernel - Re: [PATCH v3 RESEND 10/13] dt-bindings: riscv: Add Andes PMU extension description

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Thu, 26 Oct 2023 15:09:30 +0100
From:   Conor Dooley <conor@...nel.org>
To:     Yu-Chien Peter Lin <peterlin@...estech.com>
Cc:     acme@...nel.org, adrian.hunter@...el.com, ajones@...tanamicro.com,
        alexander.shishkin@...ux.intel.com, andre.przywara@....com,
        anup@...infault.org, aou@...s.berkeley.edu, atishp@...shpatra.org,
        conor+dt@...nel.org, conor.dooley@...rochip.com,
        devicetree@...r.kernel.org, dminus@...estech.com,
        evan@...osinc.com, geert+renesas@...der.be, guoren@...nel.org,
        heiko@...ech.de, irogers@...gle.com, jernej.skrabec@...il.com,
        jolsa@...nel.org, jszhang@...nel.org,
        krzysztof.kozlowski+dt@...aro.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-perf-users@...r.kernel.org,
        linux-renesas-soc@...r.kernel.org, linux-riscv@...ts.infradead.org,
        linux-sunxi@...ts.linux.dev, locus84@...estech.com,
        magnus.damm@...il.com, mark.rutland@....com, mingo@...hat.com,
        n.shubin@...ro.com, namhyung@...nel.org, palmer@...belt.com,
        paul.walmsley@...ive.com, peterz@...radead.org,
        prabhakar.mahadev-lad.rj@...renesas.com, rdunlap@...radead.org,
        robh+dt@...nel.org, samuel@...lland.org, sunilvl@...tanamicro.com,
        tglx@...utronix.de, tim609@...estech.com, uwu@...nowy.me,
        wens@...e.org, will@...nel.org, ycliang@...estech.com
Subject: Re: [PATCH v3 RESEND 10/13] dt-bindings: riscv: Add Andes PMU
 extension description

On Thu, Oct 26, 2023 at 04:22:22PM +0800, Yu-Chien Peter Lin wrote:
> Hi Conor,
> 
> On Mon, Oct 23, 2023 at 01:03:53PM +0100, Conor Dooley wrote:
> > On Mon, Oct 23, 2023 at 08:40:57AM +0800, Yu Chien Peter Lin wrote:
> > > Document the ISA string for Andes Technology performance monitor
> > > extension which provides counter overflow interrupt and mode
> > > filtering mechanisms.
> > > 
> > > Signed-off-by: Yu Chien Peter Lin <peterlin@...estech.com>
> > > ---
> > > Changes v2 -> v3:
> > >   - New patch
> > > ---
> > >  Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
> > >  1 file changed, 7 insertions(+)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > index 5e9291d258d5..e0694e2adbc2 100644
> > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > @@ -246,6 +246,13 @@ properties:
> > >              in commit 2e5236 ("Ztso is now ratified.") of the
> > >              riscv-isa-manual.
> > >  
> > > +        - const: xandespmu
> > > +          description:
> > > +            The Andes Technology performance monitor extension for counter overflow
> > > +            and privilege mode filtering. For more details, see Counter Related
> > > +            Registers in the AX45MP datasheet.
> > > +            https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
> > 
> > Does/will this PMU function identically on the other CPUs that support it?
> 
> Yes, I can confirm that.

If there's a more generic document available, that'd be good.
Otherwise,
Acked-by: Conor Dooley <conor.dooley@...rochip.com>

Thanks,
Conor.

Download attachment "signature.asc" of type "application/pgp-signature" (229 bytes)