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Message-ID: <7497e738-b9de-4dcb-90f8-06d6b1a86047@linaro.org>
Date: Thu, 26 Oct 2023 16:42:01 +0200
From: Neil Armstrong <neil.armstrong@...aro.org>
To: Ulf Hansson <ulf.hansson@...aro.org>,
Tomeu Vizoso <tomeu@...euvizoso.net>
Cc: linux-kernel@...r.kernel.org, Da Xue <da@...re.computer>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Kevin Hilman <khilman@...libre.com>,
Jerome Brunet <jbrunet@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-amlogic@...ts.infradead.org, linux-pm@...r.kernel.org
Subject: Re: [PATCH 2/2] pmdomain: amlogic: Fix mask for the second NNA mem PD
domain
Hi Ulf,
On 26/10/2023 16:36, Ulf Hansson wrote:
> On Mon, 16 Oct 2023 at 10:02, Tomeu Vizoso <tomeu@...euvizoso.net> wrote:
>>
>> Without this change, the NPU hangs when the 8th NN core is used.
>>
>> It matches what the out-of-tree driver does.
>>
>> Signed-off-by: Tomeu Vizoso <tomeu@...euvizoso.net>
>
> The change looks good to me, but I have been awaiting an ack from some
> of the platform/soc maintainers before applying.
>
> That said, it looks like we need a fixes/stable tag too. Is there a
> certain commit this fixes?
It looks good for me, you can add:
Fixes: 9a217b7e8953 ("soc: amlogic: meson-pwrc: Add NNA power domain for A311D")
and
Acked-by: Neil Armstrong <neil.armstrong@...aro.org>
Thanks,
Neil
>
> Kind regards
> Uffe
>
>> ---
>> drivers/pmdomain/amlogic/meson-ee-pwrc.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/pmdomain/amlogic/meson-ee-pwrc.c b/drivers/pmdomain/amlogic/meson-ee-pwrc.c
>> index cfb796d40d9d..0dd71cd814c5 100644
>> --- a/drivers/pmdomain/amlogic/meson-ee-pwrc.c
>> +++ b/drivers/pmdomain/amlogic/meson-ee-pwrc.c
>> @@ -228,7 +228,7 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
>>
>> static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = {
>> { G12A_HHI_NANOQ_MEM_PD_REG0, GENMASK(31, 0) },
>> - { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(23, 0) },
>> + { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(31, 0) },
>> };
>>
>> #define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \
>> --
>> 2.41.0
>>
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