linux-kernel - Re: [PATCH v4 0/4] rockchip: add GATE

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Message-ID: <ac6f04ef-97b1-3dd9-a086-772a10f0a66b@rock-chips.com>
Date:   Thu, 26 Oct 2023 10:25:43 +0800
From:   zhangqing <zhangqing@...k-chips.com>
To:     Stephen Boyd <sboyd@...nel.org>,
        Sebastian Reichel <sebastian.reichel@...labora.com>
Cc:     conor+dt@...nel.org, heiko@...ech.de, kever.yang@...k-chips.com,
        krzysztof.kozlowski+dt@...aro.org, mturquette@...libre.com,
        robh+dt@...nel.org, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-clk@...r.kernel.org,
        linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
        huangtao@...k-chips.com, andy.yan@...k-chips.com
Subject: Re: [PATCH v4 0/4] rockchip: add GATE_LINK


在 2023/10/26 5:40, Stephen Boyd 写道:
> Quoting Sebastian Reichel (2023-10-25 12:48:49)
>> Hello Stephen,
>>
>> On Mon, Oct 23, 2023 at 06:47:17PM -0700, Stephen Boyd wrote:
>>> Quoting Elaine Zhang (2023-10-18 00:01:40)
>>>> Recent Rockchip SoCs have a new hardware block called Native Interface
>>>> Unit (NIU), which gates clocks to devices behind them. These effectively
>>>> need two parent clocks.
>>>> Use GATE_LINK to handle this.
>>> Why can't pm clks be used here? The qcom clk driver has been doing that
>>> for some time now.
>>>
>>>   $ git grep pm_clk_add -- drivers/clk/qcom/
>> Maybe I'm mistaken, but as far as I can tell this is adding the
>> dependency on controller level and only works because Qualcomm
>> has multiple separate clock controllers. In the Rockchip design
>> there is only one platform device.
>>
>> Note, that the original downstream code from Rockchip actually used
>> pm_clk infrastructure by moving these clocks to separate platform
>> devices. I changed this when upstreaming the code, since that leaks
>> into DT and from DT point of view there should be only one clock
>> controller.
>>
> Why can't the rockchip driver bind to a single device node and make
> sub-devices for each clk domain and register clks for those? Maybe it
> can use the auxiliary driver infrastructure to do that?

Option 1:

Use the current patch to adapt the GATE_LINK type upstream.

The real function of GATE_LINK is implemented。

Just to improve and adapt the existing features on upstream.


Option 2:

What we use on our internal branches are:

drivers/clk/rockchip/clk-link.c

static int rockchip_clk_link_probe(struct platform_device *pdev)
{
     struct rockchip_link_clk *priv;
     struct device_node *node = pdev->dev.of_node;
     const struct of_device_id *match;
     const char *clk_name;
     const struct rockchip_link_info *link_info;
     int ret;

     match = of_match_node(rockchip_clk_link_of_match, node);
     if (!match)
         return -ENXIO;

     priv = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_link_clk),
                 GFP_KERNEL);
     if (!priv)
         return -ENOMEM;

     priv->link = match->data;

     spin_lock_init(&priv->lock);
     platform_set_drvdata(pdev, priv);

     priv->base = of_iomap(node, 0);
     if (IS_ERR(priv->base))
         return PTR_ERR(priv->base);

     if (of_property_read_string(node, "clock-output-names", &clk_name))
         priv->name = node->name;
     else
         priv->name = clk_name;

     link_info = rockchip_get_link_infos(priv->link, priv->name);
     priv->shift = link_info->shift;
     priv->pname = link_info->pname;

     pm_runtime_enable(&pdev->dev);
     ret = pm_clk_create(&pdev->dev);
     if (ret)
         goto disable_pm_runtime;

     ret = pm_clk_add(&pdev->dev, "link");

     if (ret)
         goto destroy_pm_clk;

     ret = register_clocks(priv, &pdev->dev);
     if (ret)
         goto destroy_pm_clk;

     return 0;

destroy_pm_clk:
     pm_clk_destroy(&pdev->dev);
disable_pm_runtime:
     pm_runtime_disable(&pdev->dev);

     return ret;
}


Both of these methods are OK. Whichever one Upstream prefers, I can 
submit it as required.

-- 
张晴
瑞芯微电子股份有限公司
Rockchip Electronics Co.,Ltd
地址：福建省福州市铜盘路软件大道89号软件园A区21号楼
Add:No.21 Building, A District, No.89 Software Boulevard Fuzhou, Fujian 350003, P.R.China
Tel:+86-0591-83991906-8601
邮编：350003
E-mail:elaine.zhang@...k-chips.com
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