[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20231027191633.GRZTwMkaiW1nyvnzzO@fat_crate.local>
Date: Fri, 27 Oct 2023 21:16:33 +0200
From: Borislav Petkov <bp@...en8.de>
To: Peter Zijlstra <peterz@...radead.org>
Cc: X86 ML <x86@...nel.org>,
Kishon VijayAbraham <Kishon.VijayAbraham@....com>,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/2] x86/barrier: Do not serialize MSR accesses on AMD
On Fri, Oct 27, 2023 at 08:56:41PM +0200, Peter Zijlstra wrote:
> Well, you see, AFAICT the non-serializing MSRs thing is an Intel thing,
> so everything !Intel wants this gone, no?
>
> Definitely the Hygon thing wants this right along with AMD, because
> that's basically AMD, no?
Because of
ce4e240c279a ("x86: add x2apic_wrmsr_fence() to x2apic flush tlb paths")
and it being there since 2009 and getting called unconditionally.
Hygon sure, but the other vendors? I can't even test on some.
Thus the more conservative approach here.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
Powered by blists - more mailing lists