linux-kernel - [PATCH v2 00/11] riscv: ASID-related and UP-related TLB flush enhancements

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-ID: <20231028231339.3116618-1-samuel.holland@sifive.com>
Date:   Sat, 28 Oct 2023 16:11:58 -0700
From:   Samuel Holland <samuel.holland@...ive.com>
To:     Palmer Dabbelt <palmer@...belt.com>,
        Alexandre Ghiti <alexghiti@...osinc.com>,
        linux-riscv@...ts.infradead.org
Cc:     linux-kernel@...r.kernel.org, linux-mm@...ck.org,
        Samuel Holland <samuel.holland@...ive.com>
Subject: [PATCH v2 00/11] riscv: ASID-related and UP-related TLB flush enhancements

While reviewing Alexandre Ghiti's "riscv: tlb flush improvements"
series[1], I noticed that most TLB flush functions end up as a call to
local_flush_tlb_all() when SMP is disabled. This series resolves that.
Along the way, I realized that we should be using single-ASID flushes
wherever possible, so I implemented that as well.

[1]: https://lore.kernel.org/linux-riscv/20231019140151.21629-1-alexghiti@rivosinc.com/
---
This series is based on v5 of Alexandre's changes, which I have included
here so the series can be built by the CI bots. I will rebase once his
series is merged.

Changes in v2:
 - Rebase on Alexandre's "riscv: tlb flush improvements" series v5
 - Move the SMP/UP merge earlier in the series to avoid build issues
 - Make a copy of __flush_tlb_range() instead of adding ifdefs inside
 - local_flush_tlb_all() is the only function used on !MMU (smpboot.c)

Alexandre Ghiti (4):
  riscv: Improve tlb_flush()
  riscv: Improve flush_tlb_range() for hugetlb pages
  riscv: Make __flush_tlb_range() loop over pte instead of flushing the
    whole tlb
  riscv: Improve flush_tlb_kernel_range()

Samuel Holland (7):
  riscv: mm: Combine the SMP and UP TLB flush code
  riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma
  riscv: mm: Introduce cntx2asid/cntx2version helper macros
  riscv: mm: Use a fixed layout for the MM context ID
  riscv: mm: Make asid_bits a local variable
  riscv: mm: Preserve global TLB entries when switching contexts
  riscv: mm: Always use ASID to flush MM contexts

 arch/riscv/include/asm/errata_list.h |  12 +-
 arch/riscv/include/asm/mmu.h         |   3 +
 arch/riscv/include/asm/mmu_context.h |   2 -
 arch/riscv/include/asm/sbi.h         |   3 -
 arch/riscv/include/asm/tlb.h         |   8 +-
 arch/riscv/include/asm/tlbflush.h    |  59 +++++----
 arch/riscv/kernel/sbi.c              |  32 ++---
 arch/riscv/mm/Makefile               |   5 +-
 arch/riscv/mm/context.c              |  26 ++--
 arch/riscv/mm/tlbflush.c             | 184 ++++++++++++++++-----------
 10 files changed, 186 insertions(+), 148 deletions(-)

-- 
2.42.0