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Message-ID: <20231028021559.138544-1-sboyd@kernel.org>
Date:   Fri, 27 Oct 2023 19:15:58 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Linus Torvalds <torvalds@...ux-foundation.org>
Cc:     Michael Turquette <mturquette@...libre.com>,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [GIT PULL] clk fixes for v6.6-rc7

The following changes since commit a47b44fbb13f5e7a981b4515dcddc93a321ae89c:

  clk: tegra: fix error return case for recalc_rate (2023-09-12 10:56:05 -0700)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git tags/clk-fixes-for-linus

for you to fetch changes up to 790437bbe0ef7e5cb5d091dd711c0d61d03945a5:

  clk: stm32: Fix a signedness issue in clk_stm32_composite_determine_rate() (2023-10-12 17:30:54 -0700)

----------------------------------------------------------------
Three fixes, one for the clk framework and two for clk drivers:

 - Avoid an oops in possible_parent_show() by checking for no parent
   properly when a DT index based lookup is used
 - Handle errors returned from divider_ro_round_rate() in
   clk_stm32_composite_determine_rate()
 - Fix clk_ops::determine_rate() implementation of socfpga's gateclk_ops
   that was ruining uart output because the divider was forgotten about

----------------------------------------------------------------
Alessandro Carminati (1):
      clk: Sanitize possible_parent_show to Handle Return Value of of_clk_get_parent_name

Dan Carpenter (1):
      clk: stm32: Fix a signedness issue in clk_stm32_composite_determine_rate()

Maxime Ripard (1):
      clk: socfpga: gate: Account for the divider in determine_rate

 drivers/clk/clk.c                  | 21 ++++++++++++---------
 drivers/clk/socfpga/clk-gate.c     | 27 +++++++++++++++++++++++----
 drivers/clk/stm32/clk-stm32-core.c |  2 +-
 3 files changed, 36 insertions(+), 14 deletions(-)

-- 
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git/
https://git.kernel.org/pub/scm/linux/kernel/git/sboyd/spmi.git

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