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Message-ID: <8c81718f-19ff-45ff-be91-ae2d69188c90@quicinc.com>
Date: Mon, 30 Oct 2023 14:08:33 -0700
From: Jessica Zhang <quic_jesszhan@...cinc.com>
To: John Watts <contact@...kia.org>, <dri-devel@...ts.freedesktop.org>
CC: Neil Armstrong <neil.armstrong@...aro.org>,
Sam Ravnborg <sam@...nborg.org>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Heiko Stuebner <heiko@...ech.de>,
Bjorn Andersson <andersson@...nel.org>,
Chris Morgan <macromorgan@...mail.com>,
Jagan Teki <jagan@...eble.ai>,
Linus Walleij <linus.walleij@...aro.org>,
Paul Cercueil <paul@...pouillou.net>,
Christophe Branchereau <cbranchereau@...il.com>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [RFC PATCH v4 3/7] drm/panel: nv3052c: Allow specifying registers
per panel
On 10/30/2023 12:23 AM, John Watts wrote:
> Panel initialization registers are per-display and not tied to the
> controller itself. Different panels will specify their own registers.
> Attach the sequences to the panel info struct so future panels
> can specify their own sequences.
Hi John,
Reviewed-by: Jessica Zhang <quic_jesszhan@...cinc.com>
Thanks,
Jessica Zhang
>
> Signed-off-by: John Watts <contact@...kia.org>
> ---
> .../gpu/drm/panel/panel-newvision-nv3052c.c | 24 ++++++++++++-------
> 1 file changed, 15 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
> index 90dea21f9856..b0114b5e8554 100644
> --- a/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
> +++ b/drivers/gpu/drm/panel/panel-newvision-nv3052c.c
> @@ -20,11 +20,18 @@
> #include <drm/drm_modes.h>
> #include <drm/drm_panel.h>
>
> +struct nv3052c_reg {
> + u8 cmd;
> + u8 val;
> +};
> +
> struct nv3052c_panel_info {
> const struct drm_display_mode *display_modes;
> unsigned int num_modes;
> u16 width_mm, height_mm;
> u32 bus_format, bus_flags;
> + const struct nv3052c_reg *panel_regs;
> + unsigned int panel_regs_len;
> };
>
> struct nv3052c {
> @@ -36,12 +43,7 @@ struct nv3052c {
> struct gpio_desc *reset_gpio;
> };
>
> -struct nv3052c_reg {
> - u8 cmd;
> - u8 val;
> -};
> -
> -static const struct nv3052c_reg nv3052c_panel_regs[] = {
> +static const struct nv3052c_reg ltk035c5444t_panel_regs[] = {
> // EXTC Command set enable, select page 1
> { 0xff, 0x30 }, { 0xff, 0x52 }, { 0xff, 0x01 },
> // Mostly unknown registers
> @@ -244,6 +246,8 @@ static inline struct nv3052c *to_nv3052c(struct drm_panel *panel)
> static int nv3052c_prepare(struct drm_panel *panel)
> {
> struct nv3052c *priv = to_nv3052c(panel);
> + const struct nv3052c_reg *panel_regs = priv->panel_info->panel_regs;
> + unsigned int panel_regs_len = priv->panel_info->panel_regs_len;
> struct mipi_dbi *dbi = &priv->dbi;
> unsigned int i;
> int err;
> @@ -260,9 +264,9 @@ static int nv3052c_prepare(struct drm_panel *panel)
> gpiod_set_value_cansleep(priv->reset_gpio, 0);
> usleep_range(5000, 20000);
>
> - for (i = 0; i < ARRAY_SIZE(nv3052c_panel_regs); i++) {
> - err = mipi_dbi_command(dbi, nv3052c_panel_regs[i].cmd,
> - nv3052c_panel_regs[i].val);
> + for (i = 0; i < panel_regs_len; i++) {
> + err = mipi_dbi_command(dbi, panel_regs[i].cmd,
> + panel_regs[i].val);
>
> if (err) {
> dev_err(priv->dev, "Unable to set register: %d\n", err);
> @@ -463,6 +467,8 @@ static const struct nv3052c_panel_info ltk035c5444t_panel_info = {
> .height_mm = 64,
> .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
> .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
> + .panel_regs = ltk035c5444t_panel_regs,
> + .panel_regs_len = ARRAY_SIZE(ltk035c5444t_panel_regs),
> };
>
> static const struct spi_device_id nv3052c_ids[] = {
> --
> 2.42.0
>
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