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Message-ID: <7934a36a-9438-719a-2ed0-4a78757b044b@quicinc.com>
Date: Mon, 30 Oct 2023 14:34:54 +0530
From: Mukesh Ojha <quic_mojha@...cinc.com>
To: Luca Weiss <luca.weiss@...rphone.com>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Mathieu Poirier <mathieu.poirier@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Manivannan Sadhasivam <mani@...nel.org>,
<cros-qcom-dts-watchers@...omium.org>
CC: <~postmarketos/upstreaming@...ts.sr.ht>,
<phone-devel@...r.kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Rob Herring <robh@...nel.org>,
Matti Lehtimäki <matti.lehtimaki@...il.com>,
<linux-arm-msm@...r.kernel.org>,
<linux-remoteproc@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 7/9] arm64: dts: qcom: sc7280: Add CDSP node
On 10/27/2023 7:50 PM, Luca Weiss wrote:
> Add the node for the ADSP found on the SC7280 SoC, using standard
> Qualcomm firmware.
>
> The memory region for sc7280-chrome-common.dtsi is taken from msm-5.4
> yupik.dtsi since the other areas also seem to match that file there,
> though I cannot be sure there.
>
> Signed-off-by: Luca Weiss <luca.weiss@...rphone.com>
> ---
> arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 5 +
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 138 +++++++++++++++++++++
> 2 files changed, 143 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
> index eb55616e0892..6e5a9d4c1fda 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
> @@ -29,6 +29,11 @@ adsp_mem: memory@...00000 {
> no-map;
> };
>
> + cdsp_mem: memory@...00000 {
> + reg = <0x0 0x88f00000 0x0 0x1e00000>;
> + no-map;
> + };
> +
Just a question, why to do it here, if chrome does not use this ?
-Mukesh
> camera_mem: memory@...00000 {
> reg = <0x0 0x8ad00000 0x0 0x500000>;
> no-map;
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index cc153f4e6979..e15646289bf7 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -3815,6 +3815,144 @@ nsp_noc: interconnect@...0000 {
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + remoteproc_cdsp: remoteproc@...0000 {
> + compatible = "qcom,sc7280-cdsp-pas";
> + reg = <0 0x0a300000 0 0x10000>;
> +
> + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
> + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
> + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
> + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
> + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
> + <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "wdog", "fatal", "ready", "handover",
> + "stop-ack", "shutdown-ack";
> +
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "xo";
> +
> + power-domains = <&rpmhpd SC7280_CX>,
> + <&rpmhpd SC7280_MX>;
> + power-domain-names = "cx", "mx";
> +
> + interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
> +
> + memory-region = <&cdsp_mem>;
> +
> + qcom,qmp = <&aoss_qmp>;
> +
> + qcom,smem-states = <&cdsp_smp2p_out 0>;
> + qcom,smem-state-names = "stop";
> +
> + status = "disabled";
> +
> + glink-edge {
> + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
> + IPCC_MPROC_SIGNAL_GLINK_QMP
> + IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc IPCC_CLIENT_CDSP
> + IPCC_MPROC_SIGNAL_GLINK_QMP>;
> +
> + label = "cdsp";
> + qcom,remote-pid = <5>;
> +
> + fastrpc {
> + compatible = "qcom,fastrpc";
> + qcom,glink-channels = "fastrpcglink-apps-dsp";
> + label = "cdsp";
> + qcom,non-secure-domain;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + compute-cb@1 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <1>;
> + iommus = <&apps_smmu 0x11a1 0x0420>,
> + <&apps_smmu 0x1181 0x0420>;
> + };
> +
> + compute-cb@2 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <2>;
> + iommus = <&apps_smmu 0x11a2 0x0420>,
> + <&apps_smmu 0x1182 0x0420>;
> + };
> +
> + compute-cb@3 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <3>;
> + iommus = <&apps_smmu 0x11a3 0x0420>,
> + <&apps_smmu 0x1183 0x0420>;
> + };
> +
> + compute-cb@4 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <4>;
> + iommus = <&apps_smmu 0x11a4 0x0420>,
> + <&apps_smmu 0x1184 0x0420>;
> + };
> +
> + compute-cb@5 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <5>;
> + iommus = <&apps_smmu 0x11a5 0x0420>,
> + <&apps_smmu 0x1185 0x0420>;
> + };
> +
> + compute-cb@6 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <6>;
> + iommus = <&apps_smmu 0x11a6 0x0420>,
> + <&apps_smmu 0x1186 0x0420>;
> + };
> +
> + compute-cb@7 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <7>;
> + iommus = <&apps_smmu 0x11a7 0x0420>,
> + <&apps_smmu 0x1187 0x0420>;
> + };
> +
> + compute-cb@8 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <8>;
> + iommus = <&apps_smmu 0x11a8 0x0420>,
> + <&apps_smmu 0x1188 0x0420>;
> + };
> +
> + /* note: secure cb9 in downstream */
> +
> + compute-cb@11 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <11>;
> + iommus = <&apps_smmu 0x11ab 0x0420>,
> + <&apps_smmu 0x118b 0x0420>;
> + };
> +
> + compute-cb@12 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <12>;
> + iommus = <&apps_smmu 0x11ac 0x0420>,
> + <&apps_smmu 0x118c 0x0420>;
> + };
> +
> + compute-cb@13 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <13>;
> + iommus = <&apps_smmu 0x11ad 0x0420>,
> + <&apps_smmu 0x118d 0x0420>;
> + };
> +
> + compute-cb@14 {
> + compatible = "qcom,fastrpc-compute-cb";
> + reg = <14>;
> + iommus = <&apps_smmu 0x11ae 0x0420>,
> + <&apps_smmu 0x118e 0x0420>;
> + };
> + };
> + };
> + };
> +
> usb_1: usb@...8800 {
> compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
> reg = <0 0x0a6f8800 0 0x400>;
>
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