linux-kernel - Re: [PATCH v1 2/2] dmaengine: idxd: Fix the incorrect descriptions

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Message-ID: <6b352a15-5b5e-4773-a32b-8dcefadc1297@intel.com>
Date:   Mon, 30 Oct 2023 09:00:04 -0700
From:   Dave Jiang <dave.jiang@...el.com>
To:     'Guanjun' <guanjun@...ux.alibaba.com>, <dmaengine@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <vkoul@...nel.org>,
        <tony.luck@...el.com>, <fenghua.yu@...el.com>
CC:     <jing.lin@...el.com>, <ashok.raj@...el.com>,
        <sanjay.k.kumar@...el.com>, <megha.dey@...el.com>,
        <jacob.jun.pan@...el.com>, <yi.l.liu@...el.com>,
        <tglx@...utronix.de>
Subject: Re: [PATCH v1 2/2] dmaengine: idxd: Fix the incorrect descriptions



On 10/29/23 01:00, 'Guanjun' wrote:
> From: Guanjun <guanjun@...ux.alibaba.com>
> 
> Fix the incorrect descriptions for the GRPCFG register.
> No functional changes
> 
> Signed-off-by: Guanjun <guanjun@...ux.alibaba.com>

Reviewed-by: Dave Jiang <dave.jiang@...el.com>

Thanks!

> ---
>  drivers/dma/idxd/registers.h | 13 ++++++++-----
>  1 file changed, 8 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/dma/idxd/registers.h b/drivers/dma/idxd/registers.h
> index 7b54a3939ea1..385a162a55f2 100644
> --- a/drivers/dma/idxd/registers.h
> +++ b/drivers/dma/idxd/registers.h
> @@ -440,12 +440,15 @@ union wqcfg {
>  /*
>   * This macro calculates the offset into the GRPCFG register
>   * idxd - struct idxd *
> - * n - wq id
> - * ofs - the index of the 32b dword for the config register
> + * n - group id
> + * ofs - the index of the 64b qword for the config register
>   *
> - * The WQCFG register block is divided into groups per each wq. The n index
> - * allows us to move to the register group that's for that particular wq.
> - * Each register is 32bits. The ofs gives us the number of register to access.
> + * The GRPCFG register block is divided into three different types, that
> + * includes GRPWQCFG, GRPENGCFG and GRPFLGCFG. The n index in each group
> + * allows us to move to the register group that's for that particular wq,
> + * engine or group flag.
> + * Each register is 64bits. And the ofs in GRPWQCFG gives us the number
> + * of register to access.
>   */
>  #define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\
>  					   (n) * GRPCFG_SIZE + sizeof(u64) * (ofs))