linux-kernel - Re: [PATCH 4/8] clk: qcom: ipq5332: add gpll0_out

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Message-ID: <ac223f97efea0d5077a4e3e4dbd805b4.sboyd@kernel.org>
Date:   Mon, 30 Oct 2023 11:57:06 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Conor Dooley <conor+dt@...nel.org>,
        Kathiravan Thirumoorthy <quic_kathirav@...cinc.com>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Michael Turquette <mturquette@...libre.com>,
        Richard Cochran <richardcochran@...il.com>,
        Rob Herring <robh+dt@...nel.org>, Will Deacon <will@...nel.org>
Cc:     linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        netdev@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        Kathiravan Thirumoorthy <quic_kathirav@...cinc.com>
Subject: Re: [PATCH 4/8] clk: qcom: ipq5332: add gpll0_out_aux clock

Quoting Kathiravan Thirumoorthy (2023-10-30 02:47:19)
> Add support for gpll0_out_aux clock which acts as the parent for
> certain networking subsystem (NSS) clocks.
> 
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@...cinc.com>
> ---
>  drivers/clk/qcom/gcc-ipq5332.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
> index 235849876a9a..966bb7ca8854 100644
> --- a/drivers/clk/qcom/gcc-ipq5332.c
> +++ b/drivers/clk/qcom/gcc-ipq5332.c
> @@ -87,6 +87,19 @@ static struct clk_alpha_pll_postdiv gpll0 = {
>         },
>  };
>  
> +static struct clk_alpha_pll_postdiv gpll0_out_aux = {
> +       .offset = 0x20000,
> +       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
> +       .width = 4,
> +       .clkr.hw.init = &(struct clk_init_data) {

const initdata

> +               .name = "gpll0_out_aux",
> +               .parent_hws = (const struct clk_hw *[]) {
> +                               &gpll0_main.clkr.hw },
> +               .num_parents = 1,
> +               .ops = &clk_alpha_pll_postdiv_ro_ops,
> +       },
> +};
> +
>  static struct clk_alpha_pll gpll2_main = {
>         .offset = 0x21000,
>         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],