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Message-ID: <65cc630c-1d71-48e1-b639-b92221a8d7b1@gmail.com>
Date: Tue, 31 Oct 2023 20:46:42 +0100
From: Robert Marko <robimarko@...il.com>
To: Mantas Pucka <mantas@...vices.com>,
Ulf Hansson <ulf.hansson@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Bhupesh Sharma <bhupesh.sharma@...aro.org>
Cc: Abhishek Sahu <absahu@...eaurora.org>,
Anusha Canchi Ramachandra Rao <anusharao@...eaurora.org>,
Sricharan R <sricharan@...eaurora.org>,
Sivaprakash Murugesan <sivaprak@...eaurora.org>,
linux-mmc@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-clk@...r.kernel.org
Subject: Re: [PATCH 3/3] arm64: dts: qcom: ipq6018: add SDHCI node
On 24. 04. 2023. 14:13, Mantas Pucka wrote:
> IPQ6018 has one SD/eMMC controller, add node for it.
>
> Signed-off-by: Mantas Pucka <mantas@...vices.com>
Tested-by: Robert Marko <robimarko@...il.com>
> ---
> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index 9ff4e9d45065..b129b23d68b1 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -414,6 +414,29 @@
> };
> };
>
> + sdhc_1: mmc@...4000 {
> + compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0x0 0x07804000 0x0 0x1000>,
> + <0x0 0x07805000 0x0 0x1000>,
> + <0x0 0x07808000 0x0 0x2000>;
> + reg-names = "hc", "cqhci", "ice";
> +
> + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> + <&gcc GCC_SDCC1_APPS_CLK>,
> + <&xo>,
> + <&gcc GCC_SDCC1_ICE_CORE_CLK>;
> + clock-names = "iface", "core", "xo", "ice";
> +
> + resets = <&gcc GCC_SDCC1_BCR>;
> + supports-cqe;
> + bus-width = <8>;
> + status = "disabled";
> + };
> +
> blsp_dma: dma-controller@...4000 {
> compatible = "qcom,bam-v1.7.0";
> reg = <0x0 0x07884000 0x0 0x2b000>;
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