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Message-ID: <dbdafdf5-10cd-fd66-1691-e4ec600bead5@amd.com>
Date: Tue, 31 Oct 2023 12:54:18 +0530
From: "Rao, Appana Durga Kedareswara" <appanad@....com>
To: Michal Simek <monstr@...str.eu>, kernel test robot <lkp@...el.com>,
Appana Durga Kedareswara rao <appana.durga.rao@...inx.com>
Cc: oe-kbuild-all@...ts.linux.dev, linux-kernel@...r.kernel.org,
Radhey Shyam Pandey <radhey.shyam.pandey@....com>
Subject: Re: arch/microblaze/kernel/entry.S:945: Error: unknown opcode
"suspend"
Hi Michal,
On 31/10/23 12:28 pm, Michal Simek wrote:
> CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or
> responding to this email.
>
>
> Hi Kedar,
>
> On 10/30/23 18:12, kernel test robot wrote:
>> Hi Appana,
>>
>> FYI, the error/warning still remains.
>>
>> tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
>> head: ffc253263a1375a65fa6c9f62a893e9767fbebfa
>> commit: 88707ebe77e23e856981e597f322cabbf6415662 microblaze: Add custom break vector handler for mb manager
>> date: 1 year, 1 month ago
>> config: microblaze-buildonly-randconfig-r003-20230509 (https://download.01.org/0day-ci/archive/20231031/202310310151.UhB396Qs-lkp@intel.com/config)
>> compiler: microblaze-linux-gcc (GCC) 13.2.0
>> reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231031/202310310151.UhB396Qs-lkp@intel.com/reproduce)
>>
>> If you fix the issue in a separate patch/commit (i.e. not just a new version of
>> the same patch/commit), kindly add following tags
>> | Reported-by: kernel test robot <lkp@...el.com>
>> | Closes: https://lore.kernel.org/oe-kbuild-all/202310310151.UhB396Qs-lkp@intel.com/
>>
>> All errors (new ones prefixed by >>):
>>
>> arch/microblaze/kernel/entry.S: Assembler messages:
>>>> arch/microblaze/kernel/entry.S:945: Error: unknown opcode "suspend"
>>
>>
>> vim +/suspend +945 arch/microblaze/kernel/entry.S
>>
>> 825
>> 826 /* restore all the tlb's */
>> 827 addik r3, r0, TOPHYS(tlb_skip)
>> 828 addik r6, r0, PT_TLBL0
>> 829 addik r7, r0, PT_TLBH0
>> 830 restore_tlb:
>> 831 add r6, r6, r1
>> 832 add r7, r7, r1
>> 833 lwi r2, r6, 0
>> 834 mts rtlblo, r2
>> 835 lwi r2, r7, 0
>> 836 mts rtlbhi, r2
>> 837 addik r6, r6, 4
>> 838 addik r7, r7, 4
>> 839 bgtid r3, restore_tlb
>> 840 addik r3, r3, -1
>> 841
>> 842 lwi r5, r0, TOPHYS(xmb_manager_dev)
>> 843 lwi r8, r0, TOPHYS(xmb_manager_reset_callback)
>> 844 set_vms
>> 845 /* return from reset need -8 to adjust for rtsd r15, 8 */
>> 846 addik r15, r0, ret_from_reset - 8
>> 847 rtbd r8, 0
>> 848 nop
>> 849
>> 850 ret_from_reset:
>> 851 set_bip /* Ints masked for state restore */
>> 852 VM_OFF
>> 853 /* MS: Restore all regs */
>> 854 RESTORE_REGS
>> 855 lwi r14, r1, PT_R14
>> 856 lwi r16, r1, PT_PC
>> 857 addik r1, r1, PT_SIZE + 36
>> 858 rtbd r16, 0
>> 859 nop
>> 860
>> 861 /*
>> 862 * Break handler for MB Manager. Enter to _xmb_manager_break by
>> 863 * injecting fault in one of the TMR Microblaze core.
>> 864 * FIXME: This break handler supports getting
>> 865 * called from kernel space only.
>> 866 */
>> 867 C_ENTRY(_xmb_manager_break):
>> 868 /*
>> 869 * Reserve memory in the stack for context store/restore
>> 870 * (which includes memory for storing tlbs (max two tlbs))
>> 871 */
>> 872 addik r1, r1, -PT_SIZE - 36
>> 873 swi r1, r0, xmb_manager_stackpointer
>> 874 SAVE_REGS
>> 875 swi r14, r1, PT_R14 /* rewrite saved R14 value */
>> 876 swi r16, r1, PT_PC; /* PC and r16 are the same */
>> 877
>> 878 lwi r6, r0, TOPHYS(xmb_manager_baseaddr)
>> 879 lwi r7, r0, TOPHYS(xmb_manager_crval)
>> 880 /*
>> 881 * When the break vector gets asserted because of error injection,
>> 882 * the break signal must be blocked before exiting from the
>> 883 * break handler, below code configures the tmr manager
>> 884 * control register to block break signal.
>> 885 */
>> 886 swi r7, r6, 0
>> 887
>> 888 /* Save the special purpose registers */
>> 889 mfs r2, rpid
>> 890 swi r2, r1, PT_PID
>> 891
>> 892 mfs r2, rtlbx
>> 893 swi r2, r1, PT_TLBI
>> 894
>> 895 mfs r2, rzpr
>> 896 swi r2, r1, PT_ZPR
>> 897
>> 898 #if CONFIG_XILINX_MICROBLAZE0_USE_FPU
>> 899 mfs r2, rfsr
>> 900 swi r2, r1, PT_FSR
>> 901 #endif
>> 902 mfs r2, rmsr
>> 903 swi r2, r1, PT_MSR
>> 904
>> 905 /* Save all the tlb's */
>> 906 addik r3, r0, TOPHYS(tlb_skip)
>> 907 addik r6, r0, PT_TLBL0
>> 908 addik r7, r0, PT_TLBH0
>> 909 save_tlb:
>> 910 add r6, r6, r1
>> 911 add r7, r7, r1
>> 912 mfs r2, rtlblo
>> 913 swi r2, r6, 0
>> 914 mfs r2, rtlbhi
>> 915 swi r2, r7, 0
>> 916 addik r6, r6, 4
>> 917 addik r7, r7, 4
>> 918 bgtid r3, save_tlb
>> 919 addik r3, r3, -1
>> 920
>> 921 lwi r5, r0, TOPHYS(xmb_manager_dev)
>> 922 lwi r8, r0, TOPHYS(xmb_manager_callback)
>> 923 /* return from break need -8 to adjust for rtsd r15, 8 */
>> 924 addik r15, r0, ret_from_break - 8
>> 925 rtbd r8, 0
>> 926 nop
>> 927
>> 928 ret_from_break:
>> 929 /* flush the d-cache */
>> 930 bralid r15, mb_flush_dcache
>> 931 nop
>> 932
>> 933 /*
>> 934 * To make sure microblaze i-cache is in a proper state
>> 935 * invalidate the i-cache.
>> 936 */
>> 937 bralid r15, mb_invalidate_icache
>> 938 nop
>> 939
>> 940 set_bip; /* Ints masked for state restore */
>> 941 VM_OFF;
>> 942 mbar 1
>> 943 mbar 2
>> 944 bri 4
>> > 945 suspend
>
> Older toolchain don't need to have this pseudo code.
> What about to change it like this?
>
> mbar 24 /* suspend */
Okay will test and post a patch...
Regards,
Kedar.
>
> Thanks,
> Michal
>
> --
> Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
> w: www.monstr.eu p: +42-0-721842854
> Maintainer of Linux kernel - Xilinx Microblaze
> Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs
> U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs
> TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs
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