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Message-ID: <CAJ9a7VgJAN_mPrFZ7vQLqp-GJRKrNfKirNiJYocS6ce7GfgPcw@mail.gmail.com>
Date: Wed, 1 Nov 2023 09:38:17 +0000
From: Mike Leach <mike.leach@...aro.org>
To: James Clark <james.clark@....com>
Cc: coresight@...ts.linaro.org, suzuki.poulose@....com,
anshuman.khandual@....com, stable@...r.kernel.org,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Mathieu Poirier <mathieu.poirier@...aro.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] coresight: etm4x: Fix width of CCITMIN field
On Mon, 30 Oct 2023 at 10:29, James Clark <james.clark@....com> wrote:
>
> CCITMIN is a 12 bit field and doesn't fit in a u8, so extend it to u16.
> This probably wasn't an issue previously because values higher than 255
> never occurred.
>
> But since commit 0f55b43dedcd ("coresight: etm: Override TRCIDR3.CCITMIN
> on errata affected cpus"), a comparison with 256 was done to enable the
> errata, generating the following W=1 build error:
>
> coresight-etm4x-core.c:1188:24: error: result of comparison of
> constant 256 with expression of type 'u8' (aka 'unsigned char') is
> always false [-Werror,-Wtautological-constant-out-of-range-compare]
>
> if (drvdata->ccitmin == 256)
>
> Cc: stable@...r.kernel.org
> Fixes: 54ff892b76c6 ("coresight: etm4x: splitting struct etmv4_drvdata")
> Signed-off-by: James Clark <james.clark@....com>
> ---
> drivers/hwtracing/coresight/coresight-etm4x.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 20e2e4cb7614..da17b6c49b0f 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -1036,7 +1036,7 @@ struct etmv4_drvdata {
> u8 ctxid_size;
> u8 vmid_size;
> u8 ccsize;
> - u8 ccitmin;
> + u16 ccitmin;
> u8 s_ex_level;
> u8 ns_ex_level;
> u8 q_support;
> --
> 2.34.1
>
Reviewed-by: Mike Leach <mike.leach@...aro.org>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
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