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Message-ID: <20231102054327.GH1498@sol.localdomain>
Date: Wed, 1 Nov 2023 22:43:27 -0700
From: Eric Biggers <ebiggers@...nel.org>
To: Jerry Shih <jerry.shih@...ive.com>
Cc: paul.walmsley@...ive.com, palmer@...belt.com,
aou@...s.berkeley.edu, herbert@...dor.apana.org.au,
davem@...emloft.net, andy.chiu@...ive.com, greentime.hu@...ive.com,
conor.dooley@...rochip.com, guoren@...nel.org, bjorn@...osinc.com,
heiko@...ech.de, ardb@...nel.org, phoebe.chen@...ive.com,
hongrong.hsu@...ive.com, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-crypto@...r.kernel.org
Subject: Re: [PATCH 12/12] RISC-V: crypto: add Zvkb accelerated ChaCha20
implementation
On Thu, Oct 26, 2023 at 02:36:44AM +0800, Jerry Shih wrote:
> +static struct skcipher_alg riscv64_chacha_alg_zvkb[] = { {
> + .base = {
> + .cra_name = "chacha20",
> + .cra_driver_name = "chacha20-riscv64-zvkb",
> + .cra_priority = 300,
> + .cra_blocksize = 1,
> + .cra_ctxsize = sizeof(struct chacha_ctx),
> + .cra_module = THIS_MODULE,
> + },
> + .min_keysize = CHACHA_KEY_SIZE,
> + .max_keysize = CHACHA_KEY_SIZE,
> + .ivsize = CHACHA_IV_SIZE,
> + .chunksize = CHACHA_BLOCK_SIZE,
> + .walksize = CHACHA_BLOCK_SIZE * 4,
> + .setkey = chacha20_setkey,
> + .encrypt = chacha20_encrypt,
> + .decrypt = chacha20_encrypt,
> +} };
> +
> +static inline bool check_chacha20_ext(void)
> +{
> + return riscv_isa_extension_available(NULL, ZVKB) &&
> + riscv_vector_vlen() >= 128;
> +}
> +
> +static int __init riscv64_chacha_mod_init(void)
> +{
> + if (check_chacha20_ext())
> + return crypto_register_skciphers(
> + riscv64_chacha_alg_zvkb,
> + ARRAY_SIZE(riscv64_chacha_alg_zvkb));
> +
> + return -ENODEV;
> +}
> +
> +static void __exit riscv64_chacha_mod_fini(void)
> +{
> + if (check_chacha20_ext())
> + crypto_unregister_skciphers(
> + riscv64_chacha_alg_zvkb,
> + ARRAY_SIZE(riscv64_chacha_alg_zvkb));
> +}
When there's just one algorithm being registered/unregistered,
crypto_register_skcipher() and crypto_unregister_skcipher() can be used.
> +# - RV64I
> +# - RISC-V Vector ('V') with VLEN >= 128
> +# - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
> +# - RISC-V Zicclsm(Main memory supports misaligned loads/stores)
How is the presence of the Zicclsm extension guaranteed?
- Eric
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