linux-kernel - [PATCH v3 2/4] dt-bindings: riscv: Add Svadu Entry

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [day] [month] [year] [list]

Message-Id: <20231102120129.11261-3-yongxuan.wang@sifive.com>
Date:   Thu,  2 Nov 2023 12:01:23 +0000
From:   Yong-Xuan Wang <yongxuan.wang@...ive.com>
To:     linux-riscv@...ts.infradead.org, kvm-riscv@...ts.infradead.org
Cc:     greentime.hu@...ive.com, vincent.chen@...ive.com, tjytimi@....com,
        alex@...ti.fr, conor.dooley@...rochip.com, ajones@...tanamicro.com,
        Yong-Xuan Wang <yongxuan.wang@...ive.com>,
        Conor Dooley <conor@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: [PATCH v3 2/4] dt-bindings: riscv: Add Svadu Entry

Add an entry for the Svadu extension to the riscv,isa-extensions property.

Signed-off-by: Yong-Xuan Wang <yongxuan.wang@...ive.com>
Acked-by: Conor Dooley <conor.dooley@...rochip.com>
Reviewed-by: Andrew Jones <ajones@...tanamicro.com>
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index cc1f546fdbdc..b5a0aed0165b 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -147,6 +147,12 @@ properties:
             ratified at commit 3f9ed34 ("Add ability to manually trigger
             workflow. (#2)") of riscv-time-compare.
 
+        - const: svadu
+          description: |
+            The standard Svadu supervisor-level extension for hardware updating
+            of PTE A/D bits as frozen at commit b65e07c ("move to Frozen
+            state") of riscv-svadu.
+
         - const: svinval
           description:
             The standard Svinval supervisor-level extension for fine-grained
-- 
2.17.1