[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <9a2ff779-163c-415d-9e78-84756ad77c86@quicinc.com>
Date: Fri, 3 Nov 2023 15:51:56 +0530
From: Ankit Sharma <quic_anshar@...cinc.com>
To: <cros-qcom-dts-watchers@...omium.org>, <agross@...nel.org>,
<andersson@...nel.org>, <konrad.dybcio@...aro.org>,
<robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<conor+dt@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <quic_ashayj@...cinc.com>,
<quic_atulpant@...cinc.com>, <quic_rgottimu@...cinc.com>,
<quic_shashim@...cinc.com>, <quic_pkondeti@...cinc.com>
Subject: Re: [PATCH v1] ARM: dts: msm: Add capacity and DPC properties for
sc7280 soc
On 11/3/2023 3:23 PM, Ankit Sharma wrote:
> The "capacity-dmips-mhz" and "dynamic-power-coefficient" are
> used to build Energy Model which in turn is used by EAS to take
> placement decisions.
>
> Change-Id: I57aa4b99734dc349034f84bd16b02609b4ac6e55
> Signed-off-by: Ankit Sharma <quic_anshar@...cinc.com>
> ---
Please ignore this, will resend again. Sorry for the spam.
Thanks,
Ankit
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 8601253aec70..b1890824188c 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -176,6 +176,8 @@
> &CLUSTER_SLEEP_0>;
> next-level-cache = <&L2_0>;
> operating-points-v2 = <&cpu0_opp_table>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <100>;
> interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
> <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> @@ -204,6 +206,8 @@
> &CLUSTER_SLEEP_0>;
> next-level-cache = <&L2_100>;
> operating-points-v2 = <&cpu0_opp_table>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <100>;
> interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
> <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> @@ -227,6 +231,8 @@
> &CLUSTER_SLEEP_0>;
> next-level-cache = <&L2_200>;
> operating-points-v2 = <&cpu0_opp_table>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <100>;
> interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
> <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> @@ -250,6 +256,8 @@
> &CLUSTER_SLEEP_0>;
> next-level-cache = <&L2_300>;
> operating-points-v2 = <&cpu0_opp_table>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <100>;
> interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
> <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> qcom,freq-domain = <&cpufreq_hw 0>;
> @@ -273,6 +281,8 @@
> &CLUSTER_SLEEP_0>;
> next-level-cache = <&L2_400>;
> operating-points-v2 = <&cpu4_opp_table>;
> + capacity-dmips-mhz = <1946>;
> + dynamic-power-coefficient = <520>;
> interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
> <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> qcom,freq-domain = <&cpufreq_hw 1>;
> @@ -296,6 +306,8 @@
> &CLUSTER_SLEEP_0>;
> next-level-cache = <&L2_500>;
> operating-points-v2 = <&cpu4_opp_table>;
> + capacity-dmips-mhz = <1946>;
> + dynamic-power-coefficient = <520>;
> interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
> <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> qcom,freq-domain = <&cpufreq_hw 1>;
> @@ -319,6 +331,8 @@
> &CLUSTER_SLEEP_0>;
> next-level-cache = <&L2_600>;
> operating-points-v2 = <&cpu4_opp_table>;
> + capacity-dmips-mhz = <1946>;
> + dynamic-power-coefficient = <520>;
> interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
> <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> qcom,freq-domain = <&cpufreq_hw 1>;
> @@ -342,6 +356,8 @@
> &CLUSTER_SLEEP_0>;
> next-level-cache = <&L2_700>;
> operating-points-v2 = <&cpu7_opp_table>;
> + capacity-dmips-mhz = <1985>;
> + dynamic-power-coefficient = <552>;
> interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
> <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
> qcom,freq-domain = <&cpufreq_hw 2>;
Powered by blists - more mailing lists