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Message-ID: <849f77be-7cce-4c12-9064-4344e801afa5@linux.intel.com>
Date:   Fri, 3 Nov 2023 14:59:19 +0200
From:   Jarkko Nikula <jarkko.nikula@...ux.intel.com>
To:     Tam Nguyen <tamnguyenchi@...amperecomputing.com>,
        linux-kernel@...r.kernel.org, linux-i2c@...r.kernel.org
Cc:     patches@...erecomputing.com, andriy.shevchenko@...ux.intel.com,
        mika.westerberg@...ux.intel.com, jsd@...ihalf.com,
        chuong@...amperecomputing.com, darren@...amperecomputing.com,
        stable@...r.kernel.org
Subject: Re: [PATCH v2] i2c: designware: Disable TX_EMPTY irq while waiting
 for block length byte

On 11/2/23 05:30, Tam Nguyen wrote:
> During SMBus block data read process, we have seen high interrupt rate
> because of TX_EMPTY irq status while waiting for block length byte (the
> first data byte after the address phase). The interrupt handler does not
> do anything because the internal state is kept as STATUS_WRITE_IN_PROGRESS.
> Hence, we should disable TX_EMPTY IRQ until I2C DesignWare receives
> first data byte from I2C device, then re-enable it to resume SMBus
> transaction.
> 
> It takes 0.789 ms for host to receive data length from slave.
> Without the patch, i2c_dw_isr() is called 99 times by TX_EMPTY interrupt.
> And it is none after applying the patch.
> 
> Cc: stable@...r.kernel.org
> Co-developed-by: Chuong Tran <chuong@...amperecomputing.com>
> Signed-off-by: Chuong Tran <chuong@...amperecomputing.com>
> Signed-off-by: Tam Nguyen <tamnguyenchi@...amperecomputing.com>
> ---
> v2:
> 	+ Reduce the indentations level
> 	+ Use regmap_update_bits for bitfield update
> 	+ Rewrite comment statement                     [Serge]
> 	+ Update commit message
> 	+ Add Co-developed-by tag for co-authors        [Andy]
> 
> v1:
>    https://lore.kernel.org/lkml/avd7jhwexehgbvi6euzdwvf5zvqqgjx4ozo6uxu2qpmlarvva3@sgkce3rvovwk/T/
> ---
>   drivers/i2c/busses/i2c-designware-master.c | 19 ++++++++++++++++---
>   1 file changed, 16 insertions(+), 3 deletions(-)
> 
Acked-by: Jarkko Nikula <jarkko.nikula@...ux.intel.com>

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