lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <ZUUKlK-_bWHCftS_@smile.fi.intel.com>
Date:   Fri, 3 Nov 2023 16:58:28 +0200
From:   Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To:     Mika Westerberg <mika.westerberg@...ux.intel.com>
Cc:     Chen Ni <nichen@...as.ac.cn>, lee@...nel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] mfd: intel-lpss: Fix IRQ check

On Fri, Nov 03, 2023 at 08:41:40AM +0200, Mika Westerberg wrote:
> On Thu, Nov 02, 2023 at 02:38:31PM +0200, Andy Shevchenko wrote:
> > > > > > -	if (!info || !info->mem || info->irq <= 0)
> > > > > > +	if (!info || !info->mem)
> > > > > 
> > > > > This check (info->irq <= 0) covers both "invalid" interrupt numbers
> > > > > (that's the negative errno and 0 as no interrupt) so I don't see how
> > > > > this change makes it any better and the changelog does not clarify it
> > > > > either.
> > > > 
> > > > It makes sense. The IRQ here may not be 0. We should actually fix
> > > > the PCI code to guarantee that (platform_get_irq() guarantees that
> > > > in platform driver).
> > > 
> > > Yeah but I mean the check above handles any "invalid" interrupt number
> > > just fine regardless. I don't see any point changing that.
> > 
> > The point is to have proper error code to be returned. Currently it's shadowed
> > in this check.
> 
> Looking at this more, this patch actually introduces a bug.
> 
> We pass pci_dev->irq from intel-lpss-pci.c and that comes directly from
> PCI core that assigns it in pci_read_irq(). This value is unsigned int
> for starters so it is not designed to contain an error code, secondly it
> can be 0 meaning "no IRQ" either if is SRIOV device or the interrupt
> line is not assigned. I actually think SRIOV is a possibility for future
> LPSS devices so we should be dealing with this properly.

I could argue that this patch _reveals_ the bug in PCI that needs to be
addressed.

-- 
With Best Regards,
Andy Shevchenko


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ