[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-ID: <ce2c96f9-7895-41fc-a5f9-617b79f64f96@kernel.org>
Date: Mon, 6 Nov 2023 08:53:44 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Jian Yang <jian.yang@...iatek.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Krzysztof WilczyĆski <kw@...ux.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Rob Herring <robh@...nel.org>,
Jianjun Wang <jianjun.wang@...iatek.com>
Cc: linux-pci@...r.kernel.org, linux-mediatek@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Project_Global_Chrome_Upstream_Group@...iatek.com,
Chuanjia.Liu@...iatek.com, Jieyy.Yang@...iatek.com,
Qizhong.Cheng@...iatek.com, Jianguo.Zhang@...iatek.com,
Bartosz Golaszewski <bartosz.golaszewski@...aro.org>,
Abel Vesa <abel.vesa@...aro.org>
Subject: Re: [PATCH v4 2/2] PCI: mediatek-gen3: Add power and reset control
feature for downstream component
On 06/11/2023 07:12, Jian Yang wrote:
> From: "jian.yang" <jian.yang@...iatek.com>
>
> Make MediaTek's controller driver capable of controlling power
> supplies and reset pin of a downstream component in power-on and
> power-off process.
>
> Some downstream components (e.g., a WIFI chip) may need an extra
> reset other than PERST# and their power supplies, depending on
> the requirements of platform, may need to controlled by their
> parent's driver. To meet the requirements described above, I add this
> feature to MediaTek's PCIe controller driver as an optional feature.
NAK, strong NAK. This should be done in a generic way because nothing
here is specific to Mediatek.
You just implement power sequencing of devices through quirks specific
to one controller.
Work with others to provide common solution.
https://lpc.events/event/17/contributions/1507/
Best regards,
Krzysztof
Powered by blists - more mailing lists