linux-kernel - Re: [PATCH v4 1/2] dt-bindings: PCI: mediatek-gen3: Add support for controlling power and reset

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Date:   Mon, 6 Nov 2023 09:48:51 +0100
From:   Krzysztof Kozlowski <krzk@...nel.org>
To:     Jian Yang <jian.yang@...iatek.com>,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Krzysztof Wilczyński <kw@...ux.com>,
        Lorenzo Pieralisi <lpieralisi@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Rob Herring <robh@...nel.org>,
        Jianjun Wang <jianjun.wang@...iatek.com>
Cc:     linux-pci@...r.kernel.org, linux-mediatek@...ts.infradead.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        Project_Global_Chrome_Upstream_Group@...iatek.com,
        Chuanjia.Liu@...iatek.com, Jieyy.Yang@...iatek.com,
        Qizhong.Cheng@...iatek.com, Jianguo.Zhang@...iatek.com
Subject: Re: [PATCH v4 1/2] dt-bindings: PCI: mediatek-gen3: Add support for
 controlling power and reset

On 06/11/2023 07:12, Jian Yang wrote:
> From: "jian.yang" <jian.yang@...iatek.com>
> 
> Add new properties to support control power supplies and reset pin of
> a downstream component.
> 
> Signed-off-by: jian.yang <jian.yang@...iatek.com>
> ---
>  .../bindings/pci/mediatek-pcie-gen3.yaml      | 30 +++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> index 7e8c7a2a5f9b..a4f6b48d57fa 100644
> --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> @@ -84,6 +84,26 @@ properties:
>      items:
>        enum: [ phy, mac ]
>  
> +  vpcie1v8-supply:
> +    description:
> +      The regulator phandle that provides 1.8V power from root port to a
> +      downstream component.
> +
> +  vpcie3v3-supply:
> +    description:
> +      The regulator phandle that provides 3.3V power from root port to a
> +      downstream component.

How 3.3V supply can go from root port to downstream? Do you mean that
root port is the regulator itself (regulator provider)?

Sorry, all these supplies look like hacks - stuffing PCI device
properties into the PCI controller node.

Best regards,
Krzysztof