linux-kernel - Re: [PATCH v3 3/3] clk: mediatek: mt8188-topckgen: Refactor parents for top

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Message-ID: <34b7503e-5d1e-4fd2-a909-d7f50e45c8e6@baylibre.com>
Date:   Mon, 6 Nov 2023 09:50:29 +0100
From:   Alexandre Mergnat <amergnat@...libre.com>
To:     AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>, sboyd@...nel.org
Cc:     mturquette@...libre.com, matthias.bgg@...il.com,
        wenst@...omium.org, msp@...libre.com, yangyingliang@...wei.com,
        u.kleine-koenig@...gutronix.de, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, kernel@...labora.com
Subject: Re: [PATCH v3 3/3] clk: mediatek: mt8188-topckgen: Refactor parents
 for top_dp/edp muxes


On 03/11/2023 11:25, AngeloGioacchino Del Regno wrote:
> The top_dp and top_edp muxes can be both parented to either TVDPLL1
> or TVDPLL2, two identically specced PLLs for the specific purpose of
> giving out pixel clock: this becomes a problem when the MediaTek
> DisplayPort Interface (DPI) driver tries to set the pixel clock rate.
> 
> In the usecase of two simultaneous outputs (using two controllers),
> it was seen that one of the displays would sometimes display garbled
> output (if any at all) and this was because:
>   - top_edp was set to TVDPLL1, outputting X GHz
>   - top_dp was set to TVDPLL2, outputting Y GHz
>     - mtk_dpi calls clk_set_rate(top_edp, Z GHz)
>   - top_dp is switched to TVDPLL1
>   - TVDPLL1 changes its rate, top_edp outputs the wrong rate.
>   - eDP display is garbled
> 
> To solve this issue, remove all TVDPLL1 parents from `top_dp` and
> all TVDPLL2 parents from `top_edp`, plus, necessarily switch both
> clocks to use the new MUX_GATE_CLR_SET_UPD_INDEXED() macro to be
> able to use the right bit index for the new parents list.

Reviewed-by: Alexandre Mergnat <amergnat@...libre.com>

-- 
Regards,
Alexandre