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Message-ID: <20231106085554.3237511-2-xianwei.zhao@amlogic.com>
Date: Mon, 6 Nov 2023 16:55:51 +0800
From: Xianwei Zhao <xianwei.zhao@...ogic.com>
To: <linux-arm-kernel@...ts.infradead.org>,
<linux-amlogic@...ts.infradead.org>, <linux-clk@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
CC: Neil Armstrong <neil.armstrong@...aro.org>,
Jerome Brunet <jbrunet@...libre.com>,
Michael Turquette <mturquette@...libre.com>,
"Stephen Boyd" <sboyd@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
Kevin Hilman <khilman@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
Chuan Liu <chuan.liu@...ogic.com>,
Xianwei Zhao <xianwei.zhao@...ogic.com>
Subject: [PATCH V6 1/4] dt-bindings: clock: add Amlogic C3 PLL clock controller bindings
Add the PLL clock controller dt-bindings for Amlogic C3 SoC family.
Co-developed-by: Chuan Liu <chuan.liu@...ogic.com>
Signed-off-by: Chuan Liu <chuan.liu@...ogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@...ogic.com>
---
.../bindings/clock/amlogic,c3-pll-clkc.yaml | 59 +++++++++++++++++++
.../dt-bindings/clock/amlogic,c3-pll-clkc.h | 44 ++++++++++++++
2 files changed, 103 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
create mode 100644 include/dt-bindings/clock/amlogic,c3-pll-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
new file mode 100644
index 000000000000..9ca047698045
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic C3 Serials PLL Clock Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@...aro.org>
+ - Jerome Brunet <jbrunet@...libre.com>
+ - Chuan Liu <chuan.liu@...ogic.com>
+ - Xianwei Zhao <xianwei.zhao@...ogic.com>
+
+properties:
+ compatible:
+ const: amlogic,c3-pll-clkc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: input Top pll
+ - description: input MCLK pll
+
+ clock-names:
+ items:
+ - const: top
+ - const: mpll
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ apb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@...0 {
+ compatible = "amlogic,c3-pll-clkc";
+ reg = <0x0 0x8000 0x0 0x1a4>;
+ clocks = <&clkc_periphs 0>,
+ <&clkc_periphs 1>;
+ clock-names = "top", "mpll";
+ #clock-cells = <1>;
+ };
+ };
diff --git a/include/dt-bindings/clock/amlogic,c3-pll-clkc.h b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h
new file mode 100644
index 000000000000..60df483629ed
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,c3-pll-clkc.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2023 Amlogic, Inc. All rights reserved.
+ * Author: Chuan Liu <chuan.liu@...ogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
+#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
+
+#define CLKID_FIXED_PLL_DCO 0
+#define CLKID_FIXED_PLL 1
+#define CLKID_FCLK_50M_EN 2
+#define CLKID_FCLK_50M 3
+#define CLKID_FCLK_DIV2_DIV 4
+#define CLKID_FCLK_DIV2 5
+#define CLKID_FCLK_DIV2P5_DIV 6
+#define CLKID_FCLK_DIV2P5 7
+#define CLKID_FCLK_DIV3_DIV 8
+#define CLKID_FCLK_DIV3 9
+#define CLKID_FCLK_DIV4_DIV 10
+#define CLKID_FCLK_DIV4 11
+#define CLKID_FCLK_DIV5_DIV 12
+#define CLKID_FCLK_DIV5 13
+#define CLKID_FCLK_DIV7_DIV 14
+#define CLKID_FCLK_DIV7 15
+#define CLKID_GP0_PLL_DCO 16
+#define CLKID_GP0_PLL 17
+#define CLKID_GP1_PLL_DCO 18
+#define CLKID_GP1_PLL 19
+#define CLKID_HIFI_PLL_DCO 20
+#define CLKID_HIFI_PLL 21
+#define CLKID_MCLK_PLL_DCO 22
+#define CLKID_MCLK_PLL_OD 23
+#define CLKID_MCLK_PLL 24
+#define CLKID_MCLK0_SEL 25
+#define CLKID_MCLK0_SEL_EN 26
+#define CLKID_MCLK0_DIV 27
+#define CLKID_MCLK0 28
+#define CLKID_MCLK1_SEL 29
+#define CLKID_MCLK1_SEL_EN 30
+#define CLKID_MCLK1_DIV 31
+#define CLKID_MCLK1 32
+
+#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */
--
2.39.2
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