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Message-ID: <CAA8EJpr8Y+k2FJqFfZVagWxfgsUEnZ1010-xaaUg=c6tqu8Hsw@mail.gmail.com>
Date: Tue, 7 Nov 2023 15:06:22 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Krishna chaitanya chundru <quic_krichai@...cinc.com>
Cc: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
quic_vbadigan@...cinc.com, quic_ramkri@...cinc.com,
quic_nitegupt@...cinc.com, quic_skananth@...cinc.com,
quic_vpernami@...cinc.com, quic_parass@...cinc.com
Subject: Re: [PATCH v2 2/3] phy: qcom-qmp-pcie: Add endpoint refclk control
register offset
On Tue, 7 Nov 2023 at 14:26, Krishna chaitanya chundru
<quic_krichai@...cinc.com> wrote:
>
> Some platforms needs to keep endpoint refclk always on, for this
> purpose add this offset for all the applicable phy versions.
>
> And also add reg layout for few controllers as we are adding
> endpoint refclk control register which changes based upon phy version.
>
> Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 26 +++++++++++++++++++---
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 1 +
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h | 1 +
> drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 1 +
> 4 files changed, 26 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index a63ca7424974..74d03d217ff2 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -77,6 +77,7 @@ enum qphy_reg_layout {
> QPHY_START_CTRL,
> QPHY_PCS_STATUS,
> QPHY_PCS_POWER_DOWN_CONTROL,
> + QPHY_PCS_ENDPOINT_REFCLK_CNTRL,
> /* Keep last to ensure regs_layout arrays are properly initialized */
> QPHY_LAYOUT_SIZE
> };
> @@ -93,6 +94,7 @@ static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
> [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
> [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
> [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
> + [QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_V3_PCS_ENDPOINT_REFCLK_CNTRL,
> };
>
> static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
> @@ -107,6 +109,7 @@ static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
> [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
> [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
> [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
> + [QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_CNTRL,
> };
>
> static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
> @@ -114,6 +117,23 @@ static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
> [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
> [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
> [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
> + [QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_CNTRL,
> +};
> +
> +static const unsigned int pciephy_v5_20_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
> + [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
> + [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
Nit: we should probably define V5_20 and v6_20 versions of these registers
If you were to send v3 for any reason, could you please add them?
> + [QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_CNTRL,
> +};
> +
> +static const unsigned int pciephy_v6_20_regs_layout[QPHY_LAYOUT_SIZE] = {
> + [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
> + [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
> + [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
> + [QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_CNTRL,
> };
>
> static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
> @@ -2956,7 +2976,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
> .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> .vreg_list = qmp_phy_vreg_l,
> .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> - .regs = pciephy_v5_regs_layout,
> + .regs = pciephy_v5_20_regs_layout,
>
> .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> .phy_status = PHYSTATUS_4_20,
> @@ -3012,7 +3032,7 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = {
> .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> .vreg_list = sm8550_qmp_phy_vreg_l,
> .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
> - .regs = pciephy_v5_regs_layout,
> + .regs = pciephy_v6_20_regs_layout,
>
> .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> .phy_status = PHYSTATUS_4_20,
> @@ -3047,7 +3067,7 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = {
> .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> .vreg_list = qmp_phy_vreg_l,
> .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> - .regs = pciephy_v5_regs_layout,
> + .regs = pciephy_v5_20_regs_layout,
>
> .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> .phy_status = PHYSTATUS_4_20,
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
> index a469ae2a10a1..9b166286afda 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h
> @@ -11,6 +11,7 @@
> #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
> #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14
> #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
> +#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x24
> #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54
> #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
> #define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
> index cdf8c04ea078..8b114e538a07 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
> @@ -9,6 +9,7 @@
> /* Only for QMP V5_20 PHY - PCIe PCS registers */
> #define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2 0x00c
> #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
> +#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x020
> #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
> #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
> #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h
> index e3eb08776339..f7abe95c49ad 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h
> @@ -10,6 +10,7 @@
> #define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c
> #define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018
> #define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
> +#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_CNTRL 0x020
> #define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090
> #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0
> #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108
>
> --
> 2.42.0
>
>
--
With best wishes
Dmitry
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