Message-ID: <b1b5b020-600d-48c0-aec8-c866c4c29c7a@linaro.org>
Date:   Wed, 8 Nov 2023 09:11:50 +0100
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Michal Simek <michal.simek@....com>,
        Conor Dooley <conor@...nel.org>,
        Rob Herring <robh+dt@...nel.org>
Cc:     linux-kernel@...r.kernel.org, monstr@...str.eu,
        michal.simek@...inx.com, git@...inx.com,
        Conor Dooley <conor+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        devicetree@...r.kernel.org, palmer@...belt.com
Subject: Re: [PATCH] dt-bindings: soc: Add new board description for
 MicroBlaze V

On 08/11/2023 08:16, Michal Simek wrote:
> 
> 
> On 11/7/23 22:36, Conor Dooley wrote:
>> +CC Palmer
>>
>> On Tue, Nov 07, 2023 at 01:38:15PM +0100, Krzysztof Kozlowski wrote:
>>> On 07/11/2023 13:09, Michal Simek wrote:
>>>> On 11/7/23 12:27, Krzysztof Kozlowski wrote:
>>>>> On 07/11/2023 12:09, Michal Simek wrote:
>>>>>> On 11/6/23 18:07, Conor Dooley wrote:
>>>>>>> On Mon, Nov 06, 2023 at 12:53:40PM +0100, Michal Simek wrote:
>>
>>>>>>>> +description: |
>>>>>>>> +  AMD boards with MicroBlaze V SOC
>>>>>>>> +
>>>>>>>> +properties:
>>>>>>>> +  $nodename:
>>>>>>>> +    const: '/'
>>>>>>>> +  compatible:
>>>>>>>> +    oneOf:
>>>>>>>> +      - description: AMD MicroBlaze V
>>>>>>>> +        items:
>>>>>>>> +          - const: amd,mbv
>>>>>>>
>>>>>>> You don't actually list any boards here, but instead permit having only
>>>>>>> the SoC compatible and no board one. The SoC compatible is also
>>>>>>> incredibly generic. Personally I don't think this binding makes any
>>>>>>> sense as it appears to exist as a catch all for anything using your
>>>>>>> new cores in any combination.
>>>>>>
>>>>>> I think I need to define any string for compatibility because it is standard
>>>>>> property. Because this is soft core it can be added to any board with AMD/Xilinx
>>>>>> chip. I don't have really an option to list all boards.
>>>>>
>>>>> Why? Either there is a product with this soft-core or there is not. It
>>>>> cannot be both.
>>>>
>>>> I am doing basic enablement. I am not making product. Product will be done by
>>>> our customers using this core.
>>>> There will be thousands of different configurations done by customers which will
>>>> have products with it. Also there could be hundreds configurations done on the
>>>> same board.
>>>
>>> If this is the same board, then why there is compatible for it?
>>>
>>>>
>>>> Does it make sense to have board related compatible string like this if this
>>>> evaluation board is used by a lot of customers?
>>>> "amd,kcu105-mbv-ABC-vXYZ", "amd,kcu105-mbv", "amd,mbv"
>>>
>>> I miss the point what is the hardware. Evaluation board is the hardware.
>>> If someone changes it and makes a new product, it is a new product.
>>
>> To me, this does actually make (some) sense.
>> The first compatible is "soc" + board + design.
>> The second is "soc" + board.
>> The final one is the "soc".
>>
>> I say "soc" though, because it is not a single soc - it could be any
>> configuration of these soft AMD cores on an FPGA in any quality,
>> possibly set up heterogeneously too. I don't think trying to define a
>> generic compatible for it like this makes sense as the soc part does
>> not come close to identifying a specific device.
> 
> I am fine to skip it but it is required property which has to be defined somehow.
> 
>>
>> Until someone actually creates a product that ships with this, I don't
>> think it makes sense to try and define a binding.
> 
> I disagree with this description. I am coming from FPGA world where it is too 
> late to start to deal with dt binding when you have a product.
> You are saying release the product and then start to deal with dt binding. When 
> product is released there must be stable dt binding.

I meant that creating a binding for something which is not and will not
be a product does not bring any benefits. Why do we even care to
document it? Who requires it? I don't. I don't see DTS or driver, no
need for compatible.

That's why entire discussion starts with DTS (and/or driver).

> 
>>
>> I spoke to Palmer a bit about this, and what I think would make sense is
>> if you had some sort of "reference design" bitstream that people could
>> download and run on xyz AMD devkit. If that existed, then we could
>> document that configuration etc. Otherwise you're in the same spot that
>> a lot of IP vendor stuff is, where without there being something that
>> qualifies as "real hardware" using the core, it doesn't make sense to
>> try and create bindings etc. It's the same for the various people in
>> the RISC-V community that created their own CPUs that they run on FPGAs.
> 
> Aren't all ARM FVP models enabled by SW before soc vendors put them to a real 
> chip? Is there any real product available at that time?

FVP also finished one. They do not claim they added compatible for a SoC
or CPU. And that's my impression here.

> 
> I will try to find out if there is any official plan for releasing any reference 
> design against any evaluation board with commitment to supporting it.
> 
>>>> Or I can define qemu one.
>>>> "amd,qemu-mbv", "amd,mbv"
>>>
>>> QEMU is not hardware, so not.
> 
> I am still trying to wrap my head around it. In qemu we are actually going to 
> create model for this configuration but based on what you are saying here we 
> shouldn't really have DT which describes it.
> That's why we likely end up in situation that qemu create DT description self, 
> put it to memory and u-boot/kernel will consume it. The only difference is going 
> to be that DT will be used but won't be checked against dt-schema.
> I personally prefer to have DT pass dt-schema checking and tell qemu guys, this 
> is what qemu should generate.
> But if you think that this is wrong approach I will let them generate whatever 
> they want and will just check functionality. It means u-boot won't have DT, 
> Linux won't have DT and I am done.


Sorry, I am confused now. Are we talking about real hardware or QEMU SW
model? Your description clearly said:
"AMD boards with MicroBlaze V SOC"
so QEMU is not a board. Board has a physical form, a shape. Usually flat.

> 
>>>
>>>>
>>>> I think customers should be adding their compatible string in front of generic one.
>>>
>>> To what? To evaluation board? Why?
>>>
>>>>
>>>> Years ago I have done the same thing with Microblaze where compatible is defined
>>>> as xlnx,microblaze only.
>>>
>>> Again, what is the use of such binding?
>>>
>>>> When customer take this soft core, put IPs around and
>>>> create a product they should extend it to be for example like this.
>>>> "xyz,my-product-1.0", "xlnx,microblaze";
>>>
>>> So there is a product, not evaluation board.
>>>
>>>>
>>>> And over all of years I have never seen any single customer to try to push dt
>>>> description for any Microblaze based product.
>>>>
>>>>>>
>>>>>> I am happy to change it to something else but not sure to what.
>>>>>
>>>>> Alone this compatible does not bring you anything.
>>>>
>>>> I don't agree with it. It is standard property and I have to define it somehow.
>>>
>>> The property is already defined, you do not have to define it. What you
>>> define here is the value for compatible. Why do you need to define it
>>> somehow? Who asks for that?
>>>
>>>> If not, I get an error.
>>>> .../xilinx-mbv32.dtb: /: 'compatible' is a required property
>>>
>>> So you have a board? The patches must be linked to each other, e.g.
>>> preferred way is to send them in one patchset.
>>
>> There were patches sent to U-Boot for an example configuration:
>> https://lore.kernel.org/u-boot/d488b7016e0d1b1324c64d8a8b2f033851aab6c6.1699271804.git.michal.simek@amd.com/
> 
> thx.
> 
>>
>>>> And it tells me that this risc-v compatible core runs on AMD fpga and it is
>>>> compatible with it.
>>
>> Basically, it provides no more specific information than the cpu node
>> does. From me, it's a NAK for a compatible like this that that permits
>> using it in isolation for any core configuration and combination.
> 
> I hope you agree that if we ignore compatible string for the whole DT that DT 
> describes HW is very reasonable way. It means you know what CPU is, what timer, 
> console and intc are.
> It clearly shows how MicroBlaze-V AMD design will be done for others who are 
> interested on using it.
> It also shows and explain what drivers needs to be enabled in defconfigs.
> 
> In connection to above u-boot. I can simply remove DT patch from that series (or 
> move it to readme) and just say these IPs will be used that's why I am enabling 
> them and point them to public announcement. And configure that DT will be passed 
> via address in DDR and that's it.
> But I simply think that DT is providing better view on the system.
> 
> We will of course extending our device tree generators to provide DT description 
> directly from the tool as a starting point for customers.
> 


You called the file:
"AMD boards with MicroBlaze V SOC", which means "AMD MicroBlaze V" is
the name of the SoC.

Now you create one compatible, not a list, for "AMD MicroBlaze V", so
only for the SoC. That's the discussion about. You cannot create a
final, real and working hardware with this SoC alone. To make it
working, you need to put it into some board. Now, for SW models,
probably you can... but then how do you run it? If under QEMU then show
me the QEMU machine file - I bet there are some specifics for this given
configuration. This means you have specific configuration, not a generic
SoC. And again we are at the same spot as with hardware - you could not
run the SW model without configuring it, thus you cannot run a "SoC".

Best regards,
Krzysztof

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