linux-kernel - Re: [PATCH] dt-bindings: riscv: cpus: Add AMD MicroBlaze V compatible

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Date:   Wed, 8 Nov 2023 18:35:25 +0000
From:   "Keryell, Ronan (XILINX LABS)" <ronan.keryell@....com>
To:     Rob Herring <robh@...nel.org>,
        "Simek, Michal" <michal.simek@....com>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "monstr@...str.eu" <monstr@...str.eu>,
        "michal.simek@...inx.com" <michal.simek@...inx.com>,
        "git@...inx.com" <git@...inx.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Conor Dooley <conor@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>
Subject: Re: [PATCH] dt-bindings: riscv: cpus: Add AMD MicroBlaze V compatible

On 11/8/23 09:12, Rob Herring wrote:

> On Mon, Nov 06, 2023 at 12:37:47PM +0100, Michal Simek wrote:
>> MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
>> It is hardware compatible with classic MicroBlaze processor.
> 
> How is that possible? It's a different instruction set, right? I suppose
> the IP interfaces (signals) are the same/compatible.

Coincidentally, I asked myself the same question, so I asked my former 
manager who designed the ancestor of this processor. The answer is

| It is still the same MicroBlaze pipeline just with a different
| instruction decoder up front. The “macro ops” are now RISC V
| instructions, the “micro-ops” are still the same operations in the
| various MicroBlaze pipeline stages.

So, yes, all the hardware interface is the same.
-- 
Ronan KERYELL, Research Labs / San José, California.
AMD Research and Advanced Development.