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Message-ID: <ZU2D3f6kc0MDzNR5@google.com>
Date: Thu, 9 Nov 2023 17:14:05 -0800
From: Sean Christopherson <seanjc@...gle.com>
To: Jim Mattson <jmattson@...gle.com>
Cc: Konstantin Khorenko <khorenko@...tuozzo.com>,
Paolo Bonzini <pbonzini@...hat.com>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
"H . Peter Anvin" <hpa@...or.com>, kvm@...r.kernel.org,
linux-kernel@...r.kernel.org, "Denis V. Lunev" <den@...tuozzo.com>
Subject: Re: [PATCH 0/1] KVM: x86/vPMU: Speed up vmexit for AMD Zen 4 CPUs
On Fri, Nov 10, 2023, Sean Christopherson wrote:
> On Thu, Nov 09, 2023, Jim Mattson wrote:
> > On Thu, Nov 9, 2023 at 3:42 PM Sean Christopherson <seanjc@...gle.com> wrote:
> > > static inline bool pmc_is_eventsel_match(struct kvm_pmc *pmc, u64 eventsel)
> > > {
> > > return !((pmc->eventsel ^ eventsel) & AMD64_RAW_EVENT_MASK_NB);
> > > }
> >
> > The top nybble of AMD's 3-nybble event select collides with Intel's
> > IN_TX and IN_TXCP bits. I think we can assert that the vCPU can't be
> > in a transaction if KVM is emulating an instruction, but this probably
> > merits a comment.
>
> Argh, more pre-existing crud. This is silly, the vendor mask is already in
> kvm_pmu_ops.EVENTSEL_EVENT. What's one more patch...
Ah, I see what your saying. Checking the bits is actually correct, probably through
sheer dumb luck. I'll expand the comment to cover that and the reserved bits.
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