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Message-ID: <CAPLW+4nKG3D2WmQxWJ=v3_J8y6vz26gLWC2NSSfu5gukgr2RGw@mail.gmail.com>
Date: Thu, 9 Nov 2023 19:53:28 -0600
From: Sam Protsenko <semen.protsenko@...aro.org>
To: Randy Dunlap <rdunlap@...radead.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Sylwester Nawrocki <s.nawrocki@...sung.com>,
Tomasz Figa <tomasz.figa@...il.com>,
Chanwoo Choi <cw00.choi@...sung.com>,
Alim Akhtar <alim.akhtar@...sung.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2] clk: samsung: Fix kernel-doc comments
On Thu, Nov 9, 2023 at 4:42 PM Randy Dunlap <rdunlap@...radead.org> wrote:
>
>
>
> On 11/9/23 11:09, Sam Protsenko wrote:
> > Fix some issues found in kernel-doc comments in Samsung CCF framework.
> > It makes scripts/kernel-doc happy, which can be checked with:
> >
> > $ find drivers/clk/samsung/ -name '*.[ch]' -exec \
> > scripts/kernel-doc -v -none {} \;
> >
> > Signed-off-by: Sam Protsenko <semen.protsenko@...aro.org>
> > Fixes: ddeac8d968d4 ("clk: samsung: add infrastructure to register cpu clocks")
> > Fixes: 721c42a351b1 ("clk: samsung: add common clock framework helper functions for Samsung platforms")
> > Fixes: 3ff6e0d8d64d ("clk: samsung: Add support to register rate_table for samsung plls")
> > ---
> > drivers/clk/samsung/clk-cpu.h | 2 +-
> > drivers/clk/samsung/clk.h | 9 ++++++---
> > 2 files changed, 7 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h
> > index fc9f67a3b22e..103f64193e42 100644
> > --- a/drivers/clk/samsung/clk-cpu.h
> > +++ b/drivers/clk/samsung/clk-cpu.h
> > @@ -11,7 +11,7 @@
> > #include "clk.h"
> >
> > /**
> > - * struct exynos_cpuclk_data: config data to setup cpu clocks.
> > + * struct exynos_cpuclk_cfg_data: config data to setup cpu clocks.
>
> Hm, OK, the ':' separator works. '-' is the documented separator here,
> but it's not worth updating the patch for that.
>
Thanks for reviewing, Randy! As you probably already noticed, I
updated ':' bits in patch #2. Just wanted to keep this one as minimal
as possible.
> > * @prate: frequency of the primary parent clock (in KHz).
> > * @div0: value to be programmed in the div_cpu0 register.
> > * @div1: value to be programmed in the div_cpu1 register.
>
> Reviewed-by: Randy Dunlap <rdunlap@...radead.org>
> Tested-by: Randy Dunlap <rdunlap@...radead.org>
>
> thanks.
>
> --
> ~Randy
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