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Message-ID: <c3fb1fa1-4ba6-613f-a545-79e0e4b2658f@quicinc.com>
Date: Fri, 10 Nov 2023 17:03:26 +0800
From: Can Guo <quic_cang@...cinc.com>
To: <neil.armstrong@...aro.org>, Can Guo <cang@....qualcomm.com>,
<bvanassche@....org>, <mani@...nel.org>,
<stanley.chu@...iatek.com>, <adrian.hunter@...el.com>,
<beanhuo@...ron.com>, <avri.altman@....com>,
<junwoo80.lee@...sung.com>, <martin.petersen@...cle.com>
CC: <linux-scsi@...r.kernel.org>, Andy Gross <agross@...nel.org>,
"Bjorn Andersson" <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
"open list:ARM/QUALCOMM SUPPORT" <linux-arm-msm@...r.kernel.org>,
"open list:GENERIC PHY FRAMEWORK" <linux-phy@...ts.infradead.org>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 6/7] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed
Gear 5 support for SM8550
Hi Neil,
On 11/10/2023 4:47 PM, neil.armstrong@...aro.org wrote:
> Hi,
>
> On 07/11/2023 05:46, Can Guo wrote:
>> From: Can Guo <quic_cang@...cinc.com>
>>
>> On SM8550, two sets of UFS PHY settings are provided, one set is to
>> support
>> HS-G5, another set is to support HS-G4 and lower gears. The two sets
>> of PHY
>> settings are programming different values to different registers, mixing
>> the two sets and/or overwriting one set with another set is definitely
>> not
>> blessed by UFS PHY designers. In order to add HS-G5 support for
>> SM8550, we
>> need to split the two sets into their dedicated tables, and leave only
>> the
>> common settings in the .tlbs. To have the PHY programmed with the correct
>> set of PHY settings, the submode passed to PHY driver must be either
>> HS-G4
>> or HS-G5.
>
> I guess I'll need to rebase my SM8650 UFS PHY driver to support both G4
> and G5 modes
> at some point ?
Thank for reaching out. Yes, please.
I can help review the PHY settings.
BTW, are you enabling MCQ (by adding MCQ related DT) at the same time?
Thanks,
Can Guo.
>
> Neil
>
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