linux-kernel - [RFC PATCH V2 09/38] riscv: u64ilp32: Add xlen_t in user_regs

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Message-Id: <20231112061514.2306187-10-guoren@kernel.org>
Date:   Sun, 12 Nov 2023 01:14:45 -0500
From:   guoren@...nel.org
To:     arnd@...db.de, guoren@...nel.org, palmer@...osinc.com,
        tglx@...utronix.de, conor.dooley@...rochip.com, heiko@...ech.de,
        apatel@...tanamicro.com, atishp@...shpatra.org, bjorn@...nel.org,
        paul.walmsley@...ive.com, anup@...infault.org, jiawei@...as.ac.cn,
        liweiwei@...as.ac.cn, wefu@...hat.com, U2FsdGVkX1@...il.com,
        wangjunqiang@...as.ac.cn, kito.cheng@...ive.com,
        andy.chiu@...ive.com, vincent.chen@...ive.com,
        greentime.hu@...ive.com, wuwei2016@...as.ac.cn, jrtc27@...c27.com,
        luto@...nel.org, fweimer@...hat.com, catalin.marinas@....com,
        hjl.tools@...il.com
Cc:     linux-arch@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-riscv@...ts.infradead.org, Guo Ren <guoren@...ux.alibaba.com>
Subject: [RFC PATCH V2 09/38] riscv: u64ilp32: Add xlen_t in user_regs_struct

From: Guo Ren <guoren@...ux.alibaba.com>

The u64ilp32 xlen is 64-bit, not the size of long, so change the
elements of user_regs_struct with xlen_t to match different
__riscv_xlen.

Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
Signed-off-by: Guo Ren <guoren@...nel.org>
---
 arch/riscv/include/uapi/asm/ptrace.h | 72 +++++++++++++++-------------
 1 file changed, 40 insertions(+), 32 deletions(-)

diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h
index e17c550986a6..39e8d10eebaf 100644
--- a/arch/riscv/include/uapi/asm/ptrace.h
+++ b/arch/riscv/include/uapi/asm/ptrace.h
@@ -10,6 +10,14 @@
 
 #include <linux/types.h>
 
+#if __riscv_xlen == 64
+typedef __u64 xlen_t;
+#elif __riscv_xlen == 32
+typedef __u32 xlen_t;
+#else
+#error "Unexpected __riscv_xlen"
+#endif
+
 /*
  * User-mode register state for core dumps, ptrace, sigcontext
  *
@@ -17,38 +25,38 @@
  * struct user_regs_struct must form a prefix of struct pt_regs.
  */
 struct user_regs_struct {
-	unsigned long pc;
-	unsigned long ra;
-	unsigned long sp;
-	unsigned long gp;
-	unsigned long tp;
-	unsigned long t0;
-	unsigned long t1;
-	unsigned long t2;
-	unsigned long s0;
-	unsigned long s1;
-	unsigned long a0;
-	unsigned long a1;
-	unsigned long a2;
-	unsigned long a3;
-	unsigned long a4;
-	unsigned long a5;
-	unsigned long a6;
-	unsigned long a7;
-	unsigned long s2;
-	unsigned long s3;
-	unsigned long s4;
-	unsigned long s5;
-	unsigned long s6;
-	unsigned long s7;
-	unsigned long s8;
-	unsigned long s9;
-	unsigned long s10;
-	unsigned long s11;
-	unsigned long t3;
-	unsigned long t4;
-	unsigned long t5;
-	unsigned long t6;
+	xlen_t pc;
+	xlen_t ra;
+	xlen_t sp;
+	xlen_t gp;
+	xlen_t tp;
+	xlen_t t0;
+	xlen_t t1;
+	xlen_t t2;
+	xlen_t s0;
+	xlen_t s1;
+	xlen_t a0;
+	xlen_t a1;
+	xlen_t a2;
+	xlen_t a3;
+	xlen_t a4;
+	xlen_t a5;
+	xlen_t a6;
+	xlen_t a7;
+	xlen_t s2;
+	xlen_t s3;
+	xlen_t s4;
+	xlen_t s5;
+	xlen_t s6;
+	xlen_t s7;
+	xlen_t s8;
+	xlen_t s9;
+	xlen_t s10;
+	xlen_t s11;
+	xlen_t t3;
+	xlen_t t4;
+	xlen_t t5;
+	xlen_t t6;
 };
 
 struct __riscv_f_ext_state {
-- 
2.36.1